- Generated by
1.9.1
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STM32F4xx_HAL_Driver
1.8.3
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Header file of BUS LL module. More...
Go to the source code of this file.
Functions | |
| __STATIC_INLINE void | LL_AHB1_GRP1_EnableClock (uint32_t Periphs) |
| Enable AHB1 peripherals clock. @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock. More... | |
| __STATIC_INLINE uint32_t | LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs) |
| Check if AHB1 peripheral clock is enabled or not @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock. More... | |
| __STATIC_INLINE void | LL_AHB1_GRP1_DisableClock (uint32_t Periphs) |
| Disable AHB1 peripherals clock. @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock. More... | |
| __STATIC_INLINE void | LL_AHB1_GRP1_ForceReset (uint32_t Periphs) |
| Force AHB1 peripherals reset. @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset. More... | |
| __STATIC_INLINE void | LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs) |
| Release AHB1 peripherals reset. @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset. More... | |
| __STATIC_INLINE void | LL_AHB1_GRP1_EnableClockLowPower (uint32_t Periphs) |
| Enable AHB1 peripheral clocks in low-power mode @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower. More... | |
| __STATIC_INLINE void | LL_AHB1_GRP1_DisableClockLowPower (uint32_t Periphs) |
| Disable AHB1 peripheral clocks in low-power mode @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower. More... | |
| __STATIC_INLINE void | LL_AHB2_GRP1_EnableClock (uint32_t Periphs) |
| Enable AHB2 peripherals clock. @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock AHB2ENR AESEN LL_AHB2_GRP1_EnableClock AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock. More... | |
| __STATIC_INLINE uint32_t | LL_AHB2_GRP1_IsEnabledClock (uint32_t Periphs) |
| Check if AHB2 peripheral clock is enabled or not @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock. More... | |
| __STATIC_INLINE void | LL_AHB2_GRP1_DisableClock (uint32_t Periphs) |
| Disable AHB2 peripherals clock. @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock AHB2ENR AESEN LL_AHB2_GRP1_DisableClock AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock. More... | |
| __STATIC_INLINE void | LL_AHB2_GRP1_ForceReset (uint32_t Periphs) |
| Force AHB2 peripherals reset. @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset. More... | |
| __STATIC_INLINE void | LL_AHB2_GRP1_ReleaseReset (uint32_t Periphs) |
| Release AHB2 peripherals reset. @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset. More... | |
| __STATIC_INLINE void | LL_AHB2_GRP1_EnableClockLowPower (uint32_t Periphs) |
| Enable AHB2 peripheral clocks in low-power mode @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower. More... | |
| __STATIC_INLINE void | LL_AHB2_GRP1_DisableClockLowPower (uint32_t Periphs) |
| Disable AHB2 peripheral clocks in low-power mode @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower. More... | |
| __STATIC_INLINE void | LL_AHB3_GRP1_EnableClock (uint32_t Periphs) |
| Enable AHB3 peripherals clock. @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock. More... | |
| __STATIC_INLINE uint32_t | LL_AHB3_GRP1_IsEnabledClock (uint32_t Periphs) |
| Check if AHB3 peripheral clock is enabled or not @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock. More... | |
| __STATIC_INLINE void | LL_AHB3_GRP1_DisableClock (uint32_t Periphs) |
| Disable AHB3 peripherals clock. @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock. More... | |
| __STATIC_INLINE void | LL_AHB3_GRP1_ForceReset (uint32_t Periphs) |
| Force AHB3 peripherals reset. @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset. More... | |
| __STATIC_INLINE void | LL_AHB3_GRP1_ReleaseReset (uint32_t Periphs) |
| Release AHB3 peripherals reset. @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset. More... | |
| __STATIC_INLINE void | LL_AHB3_GRP1_EnableClockLowPower (uint32_t Periphs) |
| Enable AHB3 peripheral clocks in low-power mode @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower. More... | |
| __STATIC_INLINE void | LL_AHB3_GRP1_DisableClockLowPower (uint32_t Periphs) |
| Disable AHB3 peripheral clocks in low-power mode @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower. More... | |
| __STATIC_INLINE void | LL_APB1_GRP1_EnableClock (uint32_t Periphs) |
| Enable APB1 peripherals clock. @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock APB1ENR TIM3EN LL_APB1_GRP1_EnableClock APB1ENR TIM4EN LL_APB1_GRP1_EnableClock APB1ENR TIM5EN LL_APB1_GRP1_EnableClock APB1ENR TIM6EN LL_APB1_GRP1_EnableClock APB1ENR TIM7EN LL_APB1_GRP1_EnableClock APB1ENR TIM12EN LL_APB1_GRP1_EnableClock APB1ENR TIM13EN LL_APB1_GRP1_EnableClock APB1ENR TIM14EN LL_APB1_GRP1_EnableClock APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock APB1ENR WWDGEN LL_APB1_GRP1_EnableClock APB1ENR SPI2EN LL_APB1_GRP1_EnableClock APB1ENR SPI3EN LL_APB1_GRP1_EnableClock APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock APB1ENR USART2EN LL_APB1_GRP1_EnableClock APB1ENR USART3EN LL_APB1_GRP1_EnableClock APB1ENR UART4EN LL_APB1_GRP1_EnableClock APB1ENR UART5EN LL_APB1_GRP1_EnableClock APB1ENR I2C1EN LL_APB1_GRP1_EnableClock APB1ENR I2C2EN LL_APB1_GRP1_EnableClock APB1ENR I2C3EN LL_APB1_GRP1_EnableClock APB1ENR FMPI2C1EN LL_APB1_GRP1_EnableClock APB1ENR CAN1EN LL_APB1_GRP1_EnableClock APB1ENR CAN2EN LL_APB1_GRP1_EnableClock APB1ENR CAN3EN LL_APB1_GRP1_EnableClock APB1ENR CECEN LL_APB1_GRP1_EnableClock APB1ENR PWREN LL_APB1_GRP1_EnableClock APB1ENR DACEN LL_APB1_GRP1_EnableClock APB1ENR UART7EN LL_APB1_GRP1_EnableClock APB1ENR UART8EN LL_APB1_GRP1_EnableClock APB1ENR RTCAPBEN LL_APB1_GRP1_EnableClock. More... | |
| __STATIC_INLINE uint32_t | LL_APB1_GRP1_IsEnabledClock (uint32_t Periphs) |
| Check if APB1 peripheral clock is enabled or not @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock APB1ENR FMPI2C1EN LL_APB1_GRP1_IsEnabledClock APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock APB1ENR RTCAPBEN LL_APB1_GRP1_IsEnabledClock. More... | |
| __STATIC_INLINE void | LL_APB1_GRP1_DisableClock (uint32_t Periphs) |
| Disable APB1 peripherals clock. @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock APB1ENR TIM3EN LL_APB1_GRP1_DisableClock APB1ENR TIM4EN LL_APB1_GRP1_DisableClock APB1ENR TIM5EN LL_APB1_GRP1_DisableClock APB1ENR TIM6EN LL_APB1_GRP1_DisableClock APB1ENR TIM7EN LL_APB1_GRP1_DisableClock APB1ENR TIM12EN LL_APB1_GRP1_DisableClock APB1ENR TIM13EN LL_APB1_GRP1_DisableClock APB1ENR TIM14EN LL_APB1_GRP1_DisableClock APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock APB1ENR WWDGEN LL_APB1_GRP1_DisableClock APB1ENR SPI2EN LL_APB1_GRP1_DisableClock APB1ENR SPI3EN LL_APB1_GRP1_DisableClock APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock APB1ENR USART2EN LL_APB1_GRP1_DisableClock APB1ENR USART3EN LL_APB1_GRP1_DisableClock APB1ENR UART4EN LL_APB1_GRP1_DisableClock APB1ENR UART5EN LL_APB1_GRP1_DisableClock APB1ENR I2C1EN LL_APB1_GRP1_DisableClock APB1ENR I2C2EN LL_APB1_GRP1_DisableClock APB1ENR I2C3EN LL_APB1_GRP1_DisableClock APB1ENR FMPI2C1EN LL_APB1_GRP1_DisableClock APB1ENR CAN1EN LL_APB1_GRP1_DisableClock APB1ENR CAN2EN LL_APB1_GRP1_DisableClock APB1ENR CAN3EN LL_APB1_GRP1_DisableClock APB1ENR CECEN LL_APB1_GRP1_DisableClock APB1ENR PWREN LL_APB1_GRP1_DisableClock APB1ENR DACEN LL_APB1_GRP1_DisableClock APB1ENR UART7EN LL_APB1_GRP1_DisableClock APB1ENR UART8EN LL_APB1_GRP1_DisableClock APB1ENR RTCAPBEN LL_APB1_GRP1_DisableClock. More... | |
| __STATIC_INLINE void | LL_APB1_GRP1_ForceReset (uint32_t Periphs) |
| Force APB1 peripherals reset. @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset APB1RSTR USART2RST LL_APB1_GRP1_ForceReset APB1RSTR USART3RST LL_APB1_GRP1_ForceReset APB1RSTR UART4RST LL_APB1_GRP1_ForceReset APB1RSTR UART5RST LL_APB1_GRP1_ForceReset APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset APB1RSTR FMPI2C1RST LL_APB1_GRP1_ForceReset APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset APB1RSTR CECRST LL_APB1_GRP1_ForceReset APB1RSTR PWRRST LL_APB1_GRP1_ForceReset APB1RSTR DACRST LL_APB1_GRP1_ForceReset APB1RSTR UART7RST LL_APB1_GRP1_ForceReset APB1RSTR UART8RST LL_APB1_GRP1_ForceReset. More... | |
| __STATIC_INLINE void | LL_APB1_GRP1_ReleaseReset (uint32_t Periphs) |
| Release APB1 peripherals reset. @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset APB1RSTR FMPI2C1RST LL_APB1_GRP1_ReleaseReset APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset. More... | |
| __STATIC_INLINE void | LL_APB1_GRP1_EnableClockLowPower (uint32_t Periphs) |
| Enable APB1 peripheral clocks in low-power mode @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower APB1LPENR RTCAPBLPEN LL_APB1_GRP1_EnableClockLowPower. More... | |
| __STATIC_INLINE void | LL_APB1_GRP1_DisableClockLowPower (uint32_t Periphs) |
| Disable APB1 peripheral clocks in low-power mode @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower APB1LPENR RTCAPBLPEN LL_APB1_GRP1_DisableClockLowPower. More... | |
| __STATIC_INLINE void | LL_APB2_GRP1_EnableClock (uint32_t Periphs) |
| Enable APB2 peripherals clock. @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock APB2ENR TIM8EN LL_APB2_GRP1_EnableClock APB2ENR USART1EN LL_APB2_GRP1_EnableClock APB2ENR USART6EN LL_APB2_GRP1_EnableClock APB2ENR UART9EN LL_APB2_GRP1_EnableClock APB2ENR UART10EN LL_APB2_GRP1_EnableClock APB2ENR ADC1EN LL_APB2_GRP1_EnableClock APB2ENR ADC2EN LL_APB2_GRP1_EnableClock APB2ENR ADC3EN LL_APB2_GRP1_EnableClock APB2ENR SDIOEN LL_APB2_GRP1_EnableClock APB2ENR SPI1EN LL_APB2_GRP1_EnableClock APB2ENR SPI4EN LL_APB2_GRP1_EnableClock APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock APB2ENR EXTITEN LL_APB2_GRP1_EnableClock APB2ENR TIM9EN LL_APB2_GRP1_EnableClock APB2ENR TIM10EN LL_APB2_GRP1_EnableClock APB2ENR TIM11EN LL_APB2_GRP1_EnableClock APB2ENR SPI5EN LL_APB2_GRP1_EnableClock APB2ENR SPI6EN LL_APB2_GRP1_EnableClock APB2ENR SAI1EN LL_APB2_GRP1_EnableClock APB2ENR SAI2EN LL_APB2_GRP1_EnableClock APB2ENR LTDCEN LL_APB2_GRP1_EnableClock APB2ENR DSIEN LL_APB2_GRP1_EnableClock APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock APB2ENR DFSDM2EN LL_APB2_GRP1_EnableClock. More... | |
| __STATIC_INLINE uint32_t | LL_APB2_GRP1_IsEnabledClock (uint32_t Periphs) |
| Check if APB2 peripheral clock is enabled or not @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock APB2ENR UART10EN LL_APB2_GRP1_IsEnabledClock APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock APB2ENR EXTITEN LL_APB2_GRP1_IsEnabledClock APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock APB2ENR DFSDM2EN LL_APB2_GRP1_IsEnabledClock. More... | |
| __STATIC_INLINE void | LL_APB2_GRP1_DisableClock (uint32_t Periphs) |
| Disable APB2 peripherals clock. @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock APB2ENR TIM8EN LL_APB2_GRP1_DisableClock APB2ENR USART1EN LL_APB2_GRP1_DisableClock APB2ENR USART6EN LL_APB2_GRP1_DisableClock APB2ENR UART9EN LL_APB2_GRP1_DisableClock APB2ENR UART10EN LL_APB2_GRP1_DisableClock APB2ENR ADC1EN LL_APB2_GRP1_DisableClock APB2ENR ADC2EN LL_APB2_GRP1_DisableClock APB2ENR ADC3EN LL_APB2_GRP1_DisableClock APB2ENR SDIOEN LL_APB2_GRP1_DisableClock APB2ENR SPI1EN LL_APB2_GRP1_DisableClock APB2ENR SPI4EN LL_APB2_GRP1_DisableClock APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock APB2ENR EXTITEN LL_APB2_GRP1_DisableClock APB2ENR TIM9EN LL_APB2_GRP1_DisableClock APB2ENR TIM10EN LL_APB2_GRP1_DisableClock APB2ENR TIM11EN LL_APB2_GRP1_DisableClock APB2ENR SPI5EN LL_APB2_GRP1_DisableClock APB2ENR SPI6EN LL_APB2_GRP1_DisableClock APB2ENR SAI1EN LL_APB2_GRP1_DisableClock APB2ENR SAI2EN LL_APB2_GRP1_DisableClock APB2ENR LTDCEN LL_APB2_GRP1_DisableClock APB2ENR DSIEN LL_APB2_GRP1_DisableClock APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock APB2ENR DFSDM2EN LL_APB2_GRP1_DisableClock. More... | |
| __STATIC_INLINE void | LL_APB2_GRP1_ForceReset (uint32_t Periphs) |
| Force APB2 peripherals reset. @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset APB2RSTR USART1RST LL_APB2_GRP1_ForceReset APB2RSTR USART6RST LL_APB2_GRP1_ForceReset APB2RSTR UART9RST LL_APB2_GRP1_ForceReset APB2RSTR UART10RST LL_APB2_GRP1_ForceReset APB2RSTR ADCRST LL_APB2_GRP1_ForceReset APB2RSTR SDIORST LL_APB2_GRP1_ForceReset APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset APB2RSTR DSIRST LL_APB2_GRP1_ForceReset APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset APB2RSTR DFSDM2RST LL_APB2_GRP1_ForceReset. More... | |
| __STATIC_INLINE void | LL_APB2_GRP1_ReleaseReset (uint32_t Periphs) |
| Release APB2 peripherals reset. @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset APB2RSTR UART9RST LL_APB2_GRP1_ReleaseReset APB2RSTR UART10RST LL_APB2_GRP1_ReleaseReset APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset APB2RSTR DFSDM2RST LL_APB2_GRP1_ReleaseReset. More... | |
| __STATIC_INLINE void | LL_APB2_GRP1_EnableClockLowPower (uint32_t Periphs) |
| Enable APB2 peripheral clocks in low-power mode @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR UART9LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR UART10LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR EXTITLPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower APB2LPENR DFSDM2LPEN LL_APB2_GRP1_EnableClockLowPower. More... | |
| __STATIC_INLINE void | LL_APB2_GRP1_DisableClockLowPower (uint32_t Periphs) |
| Disable APB2 peripheral clocks in low-power mode @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR UART9LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR UART10LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR EXTITLPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower APB2LPENR DFSDM2LPEN LL_APB2_GRP1_DisableClockLowPower. More... | |
Header file of BUS LL module.
##### RCC Limitations #####
==============================================================================
[..]
A delay between an RCC peripheral clock enable and the effective peripheral
enabling should be taken into account in order to manage the peripheral read/write
from/to registers.
(+) This delay depends on the peripheral mapping.
(++) AHB & APB peripherals, 1 dummy read is necessary
[..]
Workarounds:
(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
inserted in each LL_{BUS}_GRP{x}_EnableClock() function.Copyright (c) 2017 STMicroelectronics. All rights reserved.
This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.
Definition in file stm32f4xx_ll_bus.h.
1.9.1