STM32F4xx_HAL_Driver  1.8.3
Functions
AHB1
STM32F4xx_LL_Driver » BUS » BUS Exported Functions
+ Collaboration diagram for AHB1:

Functions

__STATIC_INLINE void LL_AHB1_GRP1_EnableClock (uint32_t Periphs)
 Enable AHB1 peripherals clock. @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock
AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock
AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock
AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock
AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock
AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock
AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock
AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock
AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock
AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock
AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock
AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock
AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock
AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock. More...
 
__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock (uint32_t Periphs)
 Check if AHB1 peripheral clock is enabled or not @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock. More...
 
__STATIC_INLINE void LL_AHB1_GRP1_DisableClock (uint32_t Periphs)
 Disable AHB1 peripherals clock. @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock
AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock
AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock
AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock
AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock
AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock
AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock
AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock
AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock
AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock
AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock
AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock
AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock
AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock. More...
 
__STATIC_INLINE void LL_AHB1_GRP1_ForceReset (uint32_t Periphs)
 Force AHB1 peripherals reset. @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset
AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset
AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset
AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset
AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset. More...
 
__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset (uint32_t Periphs)
 Release AHB1 peripherals reset. @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset. More...
 
__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower (uint32_t Periphs)
 Enable AHB1 peripheral clocks in low-power mode @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower. More...
 
__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower (uint32_t Periphs)
 Disable AHB1 peripheral clocks in low-power mode @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower. More...
 

Detailed Description

Function Documentation

◆ LL_AHB1_GRP1_DisableClock()

__STATIC_INLINE void LL_AHB1_GRP1_DisableClock ( uint32_t  Periphs)

Disable AHB1 peripherals clock. @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock
AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock
AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock
AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock
AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock
AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock
AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock
AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock
AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock
AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock
AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock
AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock
AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock
AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock
AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_GPIOA
  • LL_AHB1_GRP1_PERIPH_GPIOB
  • LL_AHB1_GRP1_PERIPH_GPIOC
  • LL_AHB1_GRP1_PERIPH_GPIOD (*)
  • LL_AHB1_GRP1_PERIPH_GPIOE (*)
  • LL_AHB1_GRP1_PERIPH_GPIOF (*)
  • LL_AHB1_GRP1_PERIPH_GPIOG (*)
  • LL_AHB1_GRP1_PERIPH_GPIOH (*)
  • LL_AHB1_GRP1_PERIPH_GPIOI (*)
  • LL_AHB1_GRP1_PERIPH_GPIOJ (*)
  • LL_AHB1_GRP1_PERIPH_GPIOK (*)
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
  • LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_RNG (*)
  • LL_AHB1_GRP1_PERIPH_DMA2D (*)
  • LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
  • LL_AHB1_GRP1_PERIPH_OTGHS (*)
  • LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
(*) value not defined in all devices.
Return values
None

Definition at line 533 of file stm32f4xx_ll_bus.h.

◆ LL_AHB1_GRP1_DisableClockLowPower()

__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower ( uint32_t  Periphs)

Disable AHB1 peripheral clocks in low-power mode @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower
AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_GPIOA
  • LL_AHB1_GRP1_PERIPH_GPIOB
  • LL_AHB1_GRP1_PERIPH_GPIOC
  • LL_AHB1_GRP1_PERIPH_GPIOD (*)
  • LL_AHB1_GRP1_PERIPH_GPIOE (*)
  • LL_AHB1_GRP1_PERIPH_GPIOF (*)
  • LL_AHB1_GRP1_PERIPH_GPIOG (*)
  • LL_AHB1_GRP1_PERIPH_GPIOH (*)
  • LL_AHB1_GRP1_PERIPH_GPIOI (*)
  • LL_AHB1_GRP1_PERIPH_GPIOJ (*)
  • LL_AHB1_GRP1_PERIPH_GPIOK (*)
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
  • LL_AHB1_GRP1_PERIPH_FLITF
  • LL_AHB1_GRP1_PERIPH_SRAM1
  • LL_AHB1_GRP1_PERIPH_SRAM2 (*)
  • LL_AHB1_GRP1_PERIPH_SRAM3 (*)
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_RNG (*)
  • LL_AHB1_GRP1_PERIPH_DMA2D (*)
  • LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
  • LL_AHB1_GRP1_PERIPH_OTGHS (*)
  • LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
(*) value not defined in all devices.
Return values
None

Definition at line 769 of file stm32f4xx_ll_bus.h.

◆ LL_AHB1_GRP1_EnableClock()

__STATIC_INLINE void LL_AHB1_GRP1_EnableClock ( uint32_t  Periphs)

Enable AHB1 peripherals clock. @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock
AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock
AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock
AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock
AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock
AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock
AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock
AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock
AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock
AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock
AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock
AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock
AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock
AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock
AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_GPIOA
  • LL_AHB1_GRP1_PERIPH_GPIOB
  • LL_AHB1_GRP1_PERIPH_GPIOC
  • LL_AHB1_GRP1_PERIPH_GPIOD (*)
  • LL_AHB1_GRP1_PERIPH_GPIOE (*)
  • LL_AHB1_GRP1_PERIPH_GPIOF (*)
  • LL_AHB1_GRP1_PERIPH_GPIOG (*)
  • LL_AHB1_GRP1_PERIPH_GPIOH (*)
  • LL_AHB1_GRP1_PERIPH_GPIOI (*)
  • LL_AHB1_GRP1_PERIPH_GPIOJ (*)
  • LL_AHB1_GRP1_PERIPH_GPIOK (*)
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
  • LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_RNG (*)
  • LL_AHB1_GRP1_PERIPH_DMA2D (*)
  • LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
  • LL_AHB1_GRP1_PERIPH_OTGHS (*)
  • LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
(*) value not defined in all devices.
Return values
None

Definition at line 409 of file stm32f4xx_ll_bus.h.

◆ LL_AHB1_GRP1_EnableClockLowPower()

__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower ( uint32_t  Periphs)

Enable AHB1 peripheral clocks in low-power mode @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower
AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_GPIOA
  • LL_AHB1_GRP1_PERIPH_GPIOB
  • LL_AHB1_GRP1_PERIPH_GPIOC
  • LL_AHB1_GRP1_PERIPH_GPIOD (*)
  • LL_AHB1_GRP1_PERIPH_GPIOE (*)
  • LL_AHB1_GRP1_PERIPH_GPIOF (*)
  • LL_AHB1_GRP1_PERIPH_GPIOG (*)
  • LL_AHB1_GRP1_PERIPH_GPIOH (*)
  • LL_AHB1_GRP1_PERIPH_GPIOI (*)
  • LL_AHB1_GRP1_PERIPH_GPIOJ (*)
  • LL_AHB1_GRP1_PERIPH_GPIOK (*)
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
  • LL_AHB1_GRP1_PERIPH_FLITF
  • LL_AHB1_GRP1_PERIPH_SRAM1
  • LL_AHB1_GRP1_PERIPH_SRAM2 (*)
  • LL_AHB1_GRP1_PERIPH_SRAM3 (*)
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_RNG (*)
  • LL_AHB1_GRP1_PERIPH_DMA2D (*)
  • LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
  • LL_AHB1_GRP1_PERIPH_OTGHS (*)
  • LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
(*) value not defined in all devices.
Return values
None

Definition at line 698 of file stm32f4xx_ll_bus.h.

◆ LL_AHB1_GRP1_ForceReset()

__STATIC_INLINE void LL_AHB1_GRP1_ForceReset ( uint32_t  Periphs)

Force AHB1 peripherals reset. @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset
AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset
AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset
AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset
AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset
AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset
AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_ALL
  • LL_AHB1_GRP1_PERIPH_GPIOA
  • LL_AHB1_GRP1_PERIPH_GPIOB
  • LL_AHB1_GRP1_PERIPH_GPIOC
  • LL_AHB1_GRP1_PERIPH_GPIOD (*)
  • LL_AHB1_GRP1_PERIPH_GPIOE (*)
  • LL_AHB1_GRP1_PERIPH_GPIOF (*)
  • LL_AHB1_GRP1_PERIPH_GPIOG (*)
  • LL_AHB1_GRP1_PERIPH_GPIOH (*)
  • LL_AHB1_GRP1_PERIPH_GPIOI (*)
  • LL_AHB1_GRP1_PERIPH_GPIOJ (*)
  • LL_AHB1_GRP1_PERIPH_GPIOK (*)
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_RNG (*)
  • LL_AHB1_GRP1_PERIPH_DMA2D (*)
  • LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  • LL_AHB1_GRP1_PERIPH_OTGHS (*)
(*) value not defined in all devices.
Return values
None

Definition at line 582 of file stm32f4xx_ll_bus.h.

◆ LL_AHB1_GRP1_IsEnabledClock()

__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock ( uint32_t  Periphs)

Check if AHB1 peripheral clock is enabled or not @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock
AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_GPIOA
  • LL_AHB1_GRP1_PERIPH_GPIOB
  • LL_AHB1_GRP1_PERIPH_GPIOC
  • LL_AHB1_GRP1_PERIPH_GPIOD (*)
  • LL_AHB1_GRP1_PERIPH_GPIOE (*)
  • LL_AHB1_GRP1_PERIPH_GPIOF (*)
  • LL_AHB1_GRP1_PERIPH_GPIOG (*)
  • LL_AHB1_GRP1_PERIPH_GPIOH (*)
  • LL_AHB1_GRP1_PERIPH_GPIOI (*)
  • LL_AHB1_GRP1_PERIPH_GPIOJ (*)
  • LL_AHB1_GRP1_PERIPH_GPIOK (*)
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
  • LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_RNG (*)
  • LL_AHB1_GRP1_PERIPH_DMA2D (*)
  • LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
  • LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
  • LL_AHB1_GRP1_PERIPH_OTGHS (*)
  • LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
(*) value not defined in all devices.
Return values
Stateof Periphs (1 or 0).

Definition at line 473 of file stm32f4xx_ll_bus.h.

◆ LL_AHB1_GRP1_ReleaseReset()

__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset ( uint32_t  Periphs)

Release AHB1 peripherals reset. @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset
AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset.

Parameters
PeriphsThis parameter can be a combination of the following values:
  • LL_AHB1_GRP1_PERIPH_ALL
  • LL_AHB1_GRP1_PERIPH_GPIOA
  • LL_AHB1_GRP1_PERIPH_GPIOB
  • LL_AHB1_GRP1_PERIPH_GPIOC
  • LL_AHB1_GRP1_PERIPH_GPIOD (*)
  • LL_AHB1_GRP1_PERIPH_GPIOE (*)
  • LL_AHB1_GRP1_PERIPH_GPIOF (*)
  • LL_AHB1_GRP1_PERIPH_GPIOG (*)
  • LL_AHB1_GRP1_PERIPH_GPIOH (*)
  • LL_AHB1_GRP1_PERIPH_GPIOI (*)
  • LL_AHB1_GRP1_PERIPH_GPIOJ (*)
  • LL_AHB1_GRP1_PERIPH_GPIOK (*)
  • LL_AHB1_GRP1_PERIPH_CRC
  • LL_AHB1_GRP1_PERIPH_DMA1
  • LL_AHB1_GRP1_PERIPH_DMA2
  • LL_AHB1_GRP1_PERIPH_RNG (*)
  • LL_AHB1_GRP1_PERIPH_DMA2D (*)
  • LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  • LL_AHB1_GRP1_PERIPH_OTGHS (*)
(*) value not defined in all devices.
Return values
None

Definition at line 631 of file stm32f4xx_ll_bus.h.