STM32F4xx_HAL_Driver
1.8.3
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Data Structures | |
struct | LL_UTILS_PLLInitTypeDef |
UTILS PLL structure definition. More... | |
struct | LL_UTILS_ClkInitTypeDef |
UTILS System, AHB and APB buses clock configuration structure definition. More... | |
struct LL_UTILS_PLLInitTypeDef |
UTILS PLL structure definition.
Definition at line 94 of file stm32f4xx_ll_utils.h.
Data Fields | ||
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uint32_t | PLLM |
Division factor for PLL VCO input clock. This parameter can be a value of PLL, PLLI2S and PLLSAI division factor This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS(). |
uint32_t | PLLN |
Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = RCC_PLLN_MIN_VALUE and Max_Data = RCC_PLLN_MIN_VALUE This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS(). |
uint32_t | PLLP |
Division for the main system clock. This parameter can be a value of PLL division factor (PLLP) This feature can be modified afterwards using unitary function LL_RCC_PLL_ConfigDomain_SYS(). |
struct LL_UTILS_ClkInitTypeDef |
UTILS System, AHB and APB buses clock configuration structure definition.
Definition at line 119 of file stm32f4xx_ll_utils.h.
Data Fields | ||
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uint32_t | AHBCLKDivider |
The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). This parameter can be a value of AHB prescaler This feature can be modified afterwards using unitary function LL_RCC_SetAHBPrescaler(). |
uint32_t | APB1CLKDivider |
The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB low-speed prescaler (APB1) This feature can be modified afterwards using unitary function LL_RCC_SetAPB1Prescaler(). |
uint32_t | APB2CLKDivider |
The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). This parameter can be a value of APB high-speed prescaler (APB2) This feature can be modified afterwards using unitary function LL_RCC_SetAPB2Prescaler(). |