32 #ifndef __STM32F4xx_LL_UTILS_H
33 #define __STM32F4xx_LL_UTILS_H
40 #include "stm32f4xx.h"
59 #define LL_MAX_DELAY 0xFFFFFFFFU
64 #define UID_BASE_ADDRESS UID_BASE
69 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
74 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE
153 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U
154 #define LL_UTILS_HSEBYPASS_ON 0x00000001U
162 #define LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 0x00000000U
163 #define LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 0x00000100U
164 #define LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 0x00000200U
165 #define LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 0x00000300U
166 #define LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 0x00000400U
167 #define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 0x00000500U
168 #define LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 0x00000700U
194 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
203 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
212 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
223 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF);
241 return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
260 __STATIC_INLINE
void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
263 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL);
265 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
266 SysTick_CTRL_ENABLE_Msk;
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
Get Flash memory size.
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
Get Word0 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
Get Word1 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
Get Word2 of the unique device identifier (UID based on 96 bits)
__STATIC_INLINE uint32_t LL_GetPackageType(void)
Get Package type.
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency)
Update number of Flash wait states in line with new frequency and current voltage range.
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
This function configures system clock with HSE as clock source of the PLL.
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
This function configures the Cortex-M SysTick source of the time base.
void LL_Init1msTick(uint32_t HCLKFrequency)
This function configures the Cortex-M SysTick source to have 1ms time base.
void LL_mDelay(uint32_t Delay)
This function provides accurate delay (in milliseconds) based on SysTick counter flag.
UTILS System, AHB and APB buses clock configuration structure definition.
UTILS PLL structure definition.