PLL

Collaboration diagram for PLL:

Functions
__STATIC_INLINE void	LL_RCC_PLL_Enable (void)
	Enable PLL @rmtoll CR PLLON LL_RCC_PLL_Enable. More...
__STATIC_INLINE void	LL_RCC_PLL_Disable (void)
	Disable PLL. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_IsReady (void)
	Check if PLL Ready @rmtoll CR PLLRDY LL_RCC_PLL_IsReady. More...
__STATIC_INLINE void	LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)
	Configure PLL used for SYSCLK Domain. More...
__STATIC_INLINE void	LL_RCC_PLL_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
	Configure PLL used for 48Mhz domain clock. More...
__STATIC_INLINE void	LL_RCC_PLL_ConfigDomain_DSI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
	Configure PLL used for DSI clock. More...
__STATIC_INLINE void	LL_RCC_PLL_ConfigDomain_I2S (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
	Configure PLL used for I2S clock. More...
__STATIC_INLINE void	LL_RCC_PLL_ConfigDomain_SPDIFRX (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
	Configure PLL used for SPDIFRX clock. More...
__STATIC_INLINE void	LL_RCC_PLL_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source
	Configure PLL used for SAI clock. More...
	MODIFY_REG (RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR)
__STATIC_INLINE void	LL_RCC_PLL_SetMainSource (uint32_t PLLSource)
	Configure PLL clock source @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetMainSource (void)
	Get the oscillator used as PLL clock source. @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetN (void)
	Get Main PLL multiplication factor for VCO @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetP (void)
	Get Main PLL division factor for PLLP @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetQ (void)
	Get Main PLL division factor for PLLQ. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetR (void)
	Get Main PLL division factor for PLLR. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetDIVR (void)
	Get Main PLL division factor for PLLDIVR. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetDivider (void)
	Get Division factor for the main PLL and other PLL @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider. More...
__STATIC_INLINE void	LL_RCC_PLL_ConfigSpreadSpectrum (uint32_t Mod, uint32_t Inc, uint32_t Sel)
	Configure Spread Spectrum used for PLL. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetPeriodModulation (void)
	Get Spread Spectrum Modulation Period for PLL @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetStepIncrementation (void)
	Get Spread Spectrum Incrementation Step for PLL. More...
__STATIC_INLINE uint32_t	LL_RCC_PLL_GetSpreadSelection (void)
	Get Spread Spectrum Selection for PLL. More...
__STATIC_INLINE void	LL_RCC_PLL_SpreadSpectrum_Enable (void)
	Enable Spread Spectrum for PLL. @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable. More...
__STATIC_INLINE void	LL_RCC_PLL_SpreadSpectrum_Disable (void)
	Disable Spread Spectrum for PLL. @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable. More...

Variables
__STATIC_INLINE void uint32_t	PLLM
__STATIC_INLINE void uint32_t uint32_t	PLLN
__STATIC_INLINE void uint32_t uint32_t uint32_t	PLLR

Detailed Description

Function Documentation

LL_RCC_PLL_ConfigDomain_48M()

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLQ
	)

Configure PLL used for 48Mhz domain clock.

Note

PLL Source and PLLM Divider can be written only when PLL, PLLI2S and PLLSAI(*) are disabled

PLLN/PLLQ can be written only when PLL is disabled

This can be selected for USB, RNG, SDIO @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M
PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8 LL_RCC_PLLM_DIV_9 LL_RCC_PLLM_DIV_10 LL_RCC_PLLM_DIV_11 LL_RCC_PLLM_DIV_12 LL_RCC_PLLM_DIV_13 LL_RCC_PLLM_DIV_14 LL_RCC_PLLM_DIV_15 LL_RCC_PLLM_DIV_16 LL_RCC_PLLM_DIV_17 LL_RCC_PLLM_DIV_18 LL_RCC_PLLM_DIV_19 LL_RCC_PLLM_DIV_20 LL_RCC_PLLM_DIV_21 LL_RCC_PLLM_DIV_22 LL_RCC_PLLM_DIV_23 LL_RCC_PLLM_DIV_24 LL_RCC_PLLM_DIV_25 LL_RCC_PLLM_DIV_26 LL_RCC_PLLM_DIV_27 LL_RCC_PLLM_DIV_28 LL_RCC_PLLM_DIV_29 LL_RCC_PLLM_DIV_30 LL_RCC_PLLM_DIV_31 LL_RCC_PLLM_DIV_32 LL_RCC_PLLM_DIV_33 LL_RCC_PLLM_DIV_34 LL_RCC_PLLM_DIV_35 LL_RCC_PLLM_DIV_36 LL_RCC_PLLM_DIV_37 LL_RCC_PLLM_DIV_38 LL_RCC_PLLM_DIV_39 LL_RCC_PLLM_DIV_40 LL_RCC_PLLM_DIV_41 LL_RCC_PLLM_DIV_42 LL_RCC_PLLM_DIV_43 LL_RCC_PLLM_DIV_44 LL_RCC_PLLM_DIV_45 LL_RCC_PLLM_DIV_46 LL_RCC_PLLM_DIV_47 LL_RCC_PLLM_DIV_48 LL_RCC_PLLM_DIV_49 LL_RCC_PLLM_DIV_50 LL_RCC_PLLM_DIV_51 LL_RCC_PLLM_DIV_52 LL_RCC_PLLM_DIV_53 LL_RCC_PLLM_DIV_54 LL_RCC_PLLM_DIV_55 LL_RCC_PLLM_DIV_56 LL_RCC_PLLM_DIV_57 LL_RCC_PLLM_DIV_58 LL_RCC_PLLM_DIV_59 LL_RCC_PLLM_DIV_60 LL_RCC_PLLM_DIV_61 LL_RCC_PLLM_DIV_62 LL_RCC_PLLM_DIV_63
PLLN	Between 50/192(*) and 432 (*) value not defined in all devices.
PLLQ	This parameter can be one of the following values: LL_RCC_PLLQ_DIV_2 LL_RCC_PLLQ_DIV_3 LL_RCC_PLLQ_DIV_4 LL_RCC_PLLQ_DIV_5 LL_RCC_PLLQ_DIV_6 LL_RCC_PLLQ_DIV_7 LL_RCC_PLLQ_DIV_8 LL_RCC_PLLQ_DIV_9 LL_RCC_PLLQ_DIV_10 LL_RCC_PLLQ_DIV_11 LL_RCC_PLLQ_DIV_12 LL_RCC_PLLQ_DIV_13 LL_RCC_PLLQ_DIV_14 LL_RCC_PLLQ_DIV_15

Return values

None

Definition at line 4411 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_ConfigDomain_DSI()

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLR
	)

Configure PLL used for DSI clock.

Note

PLL Source and PLLM Divider can be written only when PLL, PLLI2S and PLLSAI are disabled

PLLN/PLLR can be written only when PLL is disabled

This can be selected for DSI @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI
PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8 LL_RCC_PLLM_DIV_9 LL_RCC_PLLM_DIV_10 LL_RCC_PLLM_DIV_11 LL_RCC_PLLM_DIV_12 LL_RCC_PLLM_DIV_13 LL_RCC_PLLM_DIV_14 LL_RCC_PLLM_DIV_15 LL_RCC_PLLM_DIV_16 LL_RCC_PLLM_DIV_17 LL_RCC_PLLM_DIV_18 LL_RCC_PLLM_DIV_19 LL_RCC_PLLM_DIV_20 LL_RCC_PLLM_DIV_21 LL_RCC_PLLM_DIV_22 LL_RCC_PLLM_DIV_23 LL_RCC_PLLM_DIV_24 LL_RCC_PLLM_DIV_25 LL_RCC_PLLM_DIV_26 LL_RCC_PLLM_DIV_27 LL_RCC_PLLM_DIV_28 LL_RCC_PLLM_DIV_29 LL_RCC_PLLM_DIV_30 LL_RCC_PLLM_DIV_31 LL_RCC_PLLM_DIV_32 LL_RCC_PLLM_DIV_33 LL_RCC_PLLM_DIV_34 LL_RCC_PLLM_DIV_35 LL_RCC_PLLM_DIV_36 LL_RCC_PLLM_DIV_37 LL_RCC_PLLM_DIV_38 LL_RCC_PLLM_DIV_39 LL_RCC_PLLM_DIV_40 LL_RCC_PLLM_DIV_41 LL_RCC_PLLM_DIV_42 LL_RCC_PLLM_DIV_43 LL_RCC_PLLM_DIV_44 LL_RCC_PLLM_DIV_45 LL_RCC_PLLM_DIV_46 LL_RCC_PLLM_DIV_47 LL_RCC_PLLM_DIV_48 LL_RCC_PLLM_DIV_49 LL_RCC_PLLM_DIV_50 LL_RCC_PLLM_DIV_51 LL_RCC_PLLM_DIV_52 LL_RCC_PLLM_DIV_53 LL_RCC_PLLM_DIV_54 LL_RCC_PLLM_DIV_55 LL_RCC_PLLM_DIV_56 LL_RCC_PLLM_DIV_57 LL_RCC_PLLM_DIV_58 LL_RCC_PLLM_DIV_59 LL_RCC_PLLM_DIV_60 LL_RCC_PLLM_DIV_61 LL_RCC_PLLM_DIV_62 LL_RCC_PLLM_DIV_63
PLLN	Between 50 and 432
PLLR	This parameter can be one of the following values: LL_RCC_PLLR_DIV_2 LL_RCC_PLLR_DIV_3 LL_RCC_PLLR_DIV_4 LL_RCC_PLLR_DIV_5 LL_RCC_PLLR_DIV_6 LL_RCC_PLLR_DIV_7

Return values

None

Definition at line 4504 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_ConfigDomain_I2S()

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLR
	)

Configure PLL used for I2S clock.

Note

PLL Source and PLLM Divider can be written only when PLL, PLLI2S and PLLSAI are disabled

PLLN/PLLR can be written only when PLL is disabled

This can be selected for I2S @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S
PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8 LL_RCC_PLLM_DIV_9 LL_RCC_PLLM_DIV_10 LL_RCC_PLLM_DIV_11 LL_RCC_PLLM_DIV_12 LL_RCC_PLLM_DIV_13 LL_RCC_PLLM_DIV_14 LL_RCC_PLLM_DIV_15 LL_RCC_PLLM_DIV_16 LL_RCC_PLLM_DIV_17 LL_RCC_PLLM_DIV_18 LL_RCC_PLLM_DIV_19 LL_RCC_PLLM_DIV_20 LL_RCC_PLLM_DIV_21 LL_RCC_PLLM_DIV_22 LL_RCC_PLLM_DIV_23 LL_RCC_PLLM_DIV_24 LL_RCC_PLLM_DIV_25 LL_RCC_PLLM_DIV_26 LL_RCC_PLLM_DIV_27 LL_RCC_PLLM_DIV_28 LL_RCC_PLLM_DIV_29 LL_RCC_PLLM_DIV_30 LL_RCC_PLLM_DIV_31 LL_RCC_PLLM_DIV_32 LL_RCC_PLLM_DIV_33 LL_RCC_PLLM_DIV_34 LL_RCC_PLLM_DIV_35 LL_RCC_PLLM_DIV_36 LL_RCC_PLLM_DIV_37 LL_RCC_PLLM_DIV_38 LL_RCC_PLLM_DIV_39 LL_RCC_PLLM_DIV_40 LL_RCC_PLLM_DIV_41 LL_RCC_PLLM_DIV_42 LL_RCC_PLLM_DIV_43 LL_RCC_PLLM_DIV_44 LL_RCC_PLLM_DIV_45 LL_RCC_PLLM_DIV_46 LL_RCC_PLLM_DIV_47 LL_RCC_PLLM_DIV_48 LL_RCC_PLLM_DIV_49 LL_RCC_PLLM_DIV_50 LL_RCC_PLLM_DIV_51 LL_RCC_PLLM_DIV_52 LL_RCC_PLLM_DIV_53 LL_RCC_PLLM_DIV_54 LL_RCC_PLLM_DIV_55 LL_RCC_PLLM_DIV_56 LL_RCC_PLLM_DIV_57 LL_RCC_PLLM_DIV_58 LL_RCC_PLLM_DIV_59 LL_RCC_PLLM_DIV_60 LL_RCC_PLLM_DIV_61 LL_RCC_PLLM_DIV_62 LL_RCC_PLLM_DIV_63
PLLN	Between 50 and 432
PLLR	This parameter can be one of the following values: LL_RCC_PLLR_DIV_2 LL_RCC_PLLR_DIV_3 LL_RCC_PLLR_DIV_4 LL_RCC_PLLR_DIV_5 LL_RCC_PLLR_DIV_6 LL_RCC_PLLR_DIV_7

Return values

None

Definition at line 4598 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_ConfigDomain_SAI()

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLR,
		uint32_t	PLLDIVR
	)

Configure PLL used for SAI clock.

Note

PLL Source and PLLM Divider can be written only when PLL, PLLI2S and PLLSAI are disabled

PLLN/PLLR can be written only when PLL is disabled

This can be selected for SAI @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI
PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI
DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8 LL_RCC_PLLM_DIV_9 LL_RCC_PLLM_DIV_10 LL_RCC_PLLM_DIV_11 LL_RCC_PLLM_DIV_12 LL_RCC_PLLM_DIV_13 LL_RCC_PLLM_DIV_14 LL_RCC_PLLM_DIV_15 LL_RCC_PLLM_DIV_16 LL_RCC_PLLM_DIV_17 LL_RCC_PLLM_DIV_18 LL_RCC_PLLM_DIV_19 LL_RCC_PLLM_DIV_20 LL_RCC_PLLM_DIV_21 LL_RCC_PLLM_DIV_22 LL_RCC_PLLM_DIV_23 LL_RCC_PLLM_DIV_24 LL_RCC_PLLM_DIV_25 LL_RCC_PLLM_DIV_26 LL_RCC_PLLM_DIV_27 LL_RCC_PLLM_DIV_28 LL_RCC_PLLM_DIV_29 LL_RCC_PLLM_DIV_30 LL_RCC_PLLM_DIV_31 LL_RCC_PLLM_DIV_32 LL_RCC_PLLM_DIV_33 LL_RCC_PLLM_DIV_34 LL_RCC_PLLM_DIV_35 LL_RCC_PLLM_DIV_36 LL_RCC_PLLM_DIV_37 LL_RCC_PLLM_DIV_38 LL_RCC_PLLM_DIV_39 LL_RCC_PLLM_DIV_40 LL_RCC_PLLM_DIV_41 LL_RCC_PLLM_DIV_42 LL_RCC_PLLM_DIV_43 LL_RCC_PLLM_DIV_44 LL_RCC_PLLM_DIV_45 LL_RCC_PLLM_DIV_46 LL_RCC_PLLM_DIV_47 LL_RCC_PLLM_DIV_48 LL_RCC_PLLM_DIV_49 LL_RCC_PLLM_DIV_50 LL_RCC_PLLM_DIV_51 LL_RCC_PLLM_DIV_52 LL_RCC_PLLM_DIV_53 LL_RCC_PLLM_DIV_54 LL_RCC_PLLM_DIV_55 LL_RCC_PLLM_DIV_56 LL_RCC_PLLM_DIV_57 LL_RCC_PLLM_DIV_58 LL_RCC_PLLM_DIV_59 LL_RCC_PLLM_DIV_60 LL_RCC_PLLM_DIV_61 LL_RCC_PLLM_DIV_62 LL_RCC_PLLM_DIV_63
PLLN	Between 50 and 432
PLLR	This parameter can be one of the following values: LL_RCC_PLLR_DIV_2 LL_RCC_PLLR_DIV_3 LL_RCC_PLLR_DIV_4 LL_RCC_PLLR_DIV_5 LL_RCC_PLLR_DIV_6 LL_RCC_PLLR_DIV_7
PLLDIVR	This parameter can be one of the following values: LL_RCC_PLLDIVR_DIV_1 (*) LL_RCC_PLLDIVR_DIV_2 (*) LL_RCC_PLLDIVR_DIV_3 (*) LL_RCC_PLLDIVR_DIV_4 (*) LL_RCC_PLLDIVR_DIV_5 (*) LL_RCC_PLLDIVR_DIV_6 (*) LL_RCC_PLLDIVR_DIV_7 (*) LL_RCC_PLLDIVR_DIV_8 (*) LL_RCC_PLLDIVR_DIV_9 (*) LL_RCC_PLLDIVR_DIV_10 (*) LL_RCC_PLLDIVR_DIV_11 (*) LL_RCC_PLLDIVR_DIV_12 (*) LL_RCC_PLLDIVR_DIV_13 (*) LL_RCC_PLLDIVR_DIV_14 (*) LL_RCC_PLLDIVR_DIV_15 (*) LL_RCC_PLLDIVR_DIV_16 (*) LL_RCC_PLLDIVR_DIV_17 (*) LL_RCC_PLLDIVR_DIV_18 (*) LL_RCC_PLLDIVR_DIV_19 (*) LL_RCC_PLLDIVR_DIV_20 (*) LL_RCC_PLLDIVR_DIV_21 (*) LL_RCC_PLLDIVR_DIV_22 (*) LL_RCC_PLLDIVR_DIV_23 (*) LL_RCC_PLLDIVR_DIV_24 (*) LL_RCC_PLLDIVR_DIV_25 (*) LL_RCC_PLLDIVR_DIV_26 (*) LL_RCC_PLLDIVR_DIV_27 (*) LL_RCC_PLLDIVR_DIV_28 (*) LL_RCC_PLLDIVR_DIV_29 (*) LL_RCC_PLLDIVR_DIV_30 (*) LL_RCC_PLLDIVR_DIV_31 (*) (*) value not defined in all devices.

Return values

None

LL_RCC_PLL_ConfigDomain_SPDIFRX()

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLR
	)

Configure PLL used for SPDIFRX clock.

Note

PLL Source and PLLM Divider can be written only when PLL, PLLI2S and PLLSAI are disabled

PLLN/PLLR can be written only when PLL is disabled

This can be selected for SPDIFRX @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX
PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8 LL_RCC_PLLM_DIV_9 LL_RCC_PLLM_DIV_10 LL_RCC_PLLM_DIV_11 LL_RCC_PLLM_DIV_12 LL_RCC_PLLM_DIV_13 LL_RCC_PLLM_DIV_14 LL_RCC_PLLM_DIV_15 LL_RCC_PLLM_DIV_16 LL_RCC_PLLM_DIV_17 LL_RCC_PLLM_DIV_18 LL_RCC_PLLM_DIV_19 LL_RCC_PLLM_DIV_20 LL_RCC_PLLM_DIV_21 LL_RCC_PLLM_DIV_22 LL_RCC_PLLM_DIV_23 LL_RCC_PLLM_DIV_24 LL_RCC_PLLM_DIV_25 LL_RCC_PLLM_DIV_26 LL_RCC_PLLM_DIV_27 LL_RCC_PLLM_DIV_28 LL_RCC_PLLM_DIV_29 LL_RCC_PLLM_DIV_30 LL_RCC_PLLM_DIV_31 LL_RCC_PLLM_DIV_32 LL_RCC_PLLM_DIV_33 LL_RCC_PLLM_DIV_34 LL_RCC_PLLM_DIV_35 LL_RCC_PLLM_DIV_36 LL_RCC_PLLM_DIV_37 LL_RCC_PLLM_DIV_38 LL_RCC_PLLM_DIV_39 LL_RCC_PLLM_DIV_40 LL_RCC_PLLM_DIV_41 LL_RCC_PLLM_DIV_42 LL_RCC_PLLM_DIV_43 LL_RCC_PLLM_DIV_44 LL_RCC_PLLM_DIV_45 LL_RCC_PLLM_DIV_46 LL_RCC_PLLM_DIV_47 LL_RCC_PLLM_DIV_48 LL_RCC_PLLM_DIV_49 LL_RCC_PLLM_DIV_50 LL_RCC_PLLM_DIV_51 LL_RCC_PLLM_DIV_52 LL_RCC_PLLM_DIV_53 LL_RCC_PLLM_DIV_54 LL_RCC_PLLM_DIV_55 LL_RCC_PLLM_DIV_56 LL_RCC_PLLM_DIV_57 LL_RCC_PLLM_DIV_58 LL_RCC_PLLM_DIV_59 LL_RCC_PLLM_DIV_60 LL_RCC_PLLM_DIV_61 LL_RCC_PLLM_DIV_62 LL_RCC_PLLM_DIV_63
PLLN	Between 50 and 432
PLLR	This parameter can be one of the following values: LL_RCC_PLLR_DIV_2 LL_RCC_PLLR_DIV_3 LL_RCC_PLLR_DIV_4 LL_RCC_PLLR_DIV_5 LL_RCC_PLLR_DIV_6 LL_RCC_PLLR_DIV_7

Return values

None

Definition at line 4692 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_ConfigDomain_SYS()

__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLP_R
	)

Configure PLL used for SYSCLK Domain.

Note

PLL Source and PLLM Divider can be written only when PLL, PLLI2S and PLLSAI(*) are disabled

PLLN/PLLP can be written only when PLL is disabled @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8 LL_RCC_PLLM_DIV_9 LL_RCC_PLLM_DIV_10 LL_RCC_PLLM_DIV_11 LL_RCC_PLLM_DIV_12 LL_RCC_PLLM_DIV_13 LL_RCC_PLLM_DIV_14 LL_RCC_PLLM_DIV_15 LL_RCC_PLLM_DIV_16 LL_RCC_PLLM_DIV_17 LL_RCC_PLLM_DIV_18 LL_RCC_PLLM_DIV_19 LL_RCC_PLLM_DIV_20 LL_RCC_PLLM_DIV_21 LL_RCC_PLLM_DIV_22 LL_RCC_PLLM_DIV_23 LL_RCC_PLLM_DIV_24 LL_RCC_PLLM_DIV_25 LL_RCC_PLLM_DIV_26 LL_RCC_PLLM_DIV_27 LL_RCC_PLLM_DIV_28 LL_RCC_PLLM_DIV_29 LL_RCC_PLLM_DIV_30 LL_RCC_PLLM_DIV_31 LL_RCC_PLLM_DIV_32 LL_RCC_PLLM_DIV_33 LL_RCC_PLLM_DIV_34 LL_RCC_PLLM_DIV_35 LL_RCC_PLLM_DIV_36 LL_RCC_PLLM_DIV_37 LL_RCC_PLLM_DIV_38 LL_RCC_PLLM_DIV_39 LL_RCC_PLLM_DIV_40 LL_RCC_PLLM_DIV_41 LL_RCC_PLLM_DIV_42 LL_RCC_PLLM_DIV_43 LL_RCC_PLLM_DIV_44 LL_RCC_PLLM_DIV_45 LL_RCC_PLLM_DIV_46 LL_RCC_PLLM_DIV_47 LL_RCC_PLLM_DIV_48 LL_RCC_PLLM_DIV_49 LL_RCC_PLLM_DIV_50 LL_RCC_PLLM_DIV_51 LL_RCC_PLLM_DIV_52 LL_RCC_PLLM_DIV_53 LL_RCC_PLLM_DIV_54 LL_RCC_PLLM_DIV_55 LL_RCC_PLLM_DIV_56 LL_RCC_PLLM_DIV_57 LL_RCC_PLLM_DIV_58 LL_RCC_PLLM_DIV_59 LL_RCC_PLLM_DIV_60 LL_RCC_PLLM_DIV_61 LL_RCC_PLLM_DIV_62 LL_RCC_PLLM_DIV_63
PLLN	Between 50/192(*) and 432 (*) value not defined in all devices.
PLLP_R	This parameter can be one of the following values: LL_RCC_PLLP_DIV_2 LL_RCC_PLLP_DIV_4 LL_RCC_PLLP_DIV_6 LL_RCC_PLLP_DIV_8 LL_RCC_PLLR_DIV_2 (*) LL_RCC_PLLR_DIV_3 (*) LL_RCC_PLLR_DIV_4 (*) LL_RCC_PLLR_DIV_5 (*) LL_RCC_PLLR_DIV_6 (*) LL_RCC_PLLR_DIV_7 (*) (*) value not defined in all devices.

Return values

None

Definition at line 4305 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_ConfigSpreadSpectrum()

__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum	(	uint32_t	Mod,
		uint32_t	Inc,
		uint32_t	Sel
	)

Configure Spread Spectrum used for PLL.

Note

These bits must be written before enabling PLL @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum
SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum
SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum

Parameters

Mod	Between Min_Data=0 and Max_Data=8191
Inc	Between Min_Data=0 and Max_Data=32767
Sel	This parameter can be one of the following values: LL_RCC_SPREAD_SELECT_CENTER LL_RCC_SPREAD_SELECT_DOWN

Return values

None

Definition at line 5062 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_Disable()

__STATIC_INLINE void LL_RCC_PLL_Disable

(

void

)

Disable PLL.

Note

Cannot be disabled if the PLL clock is used as the system clock @rmtoll CR PLLON LL_RCC_PLL_Disable

Return values

None

Definition at line 4196 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_Enable()

__STATIC_INLINE void LL_RCC_PLL_Enable

(

void

)

Enable PLL @rmtoll CR PLLON LL_RCC_PLL_Enable.

Return values

None

Definition at line 4185 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_GetDivider()

__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider

(

void

)

Get Division factor for the main PLL and other PLL @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider.

Return values

Returned

value can be one of the following values: LL_RCC_PLLM_DIV_2 LL_RCC_PLLM_DIV_3 LL_RCC_PLLM_DIV_4 LL_RCC_PLLM_DIV_5 LL_RCC_PLLM_DIV_6 LL_RCC_PLLM_DIV_7 LL_RCC_PLLM_DIV_8 LL_RCC_PLLM_DIV_9 LL_RCC_PLLM_DIV_10 LL_RCC_PLLM_DIV_11 LL_RCC_PLLM_DIV_12 LL_RCC_PLLM_DIV_13 LL_RCC_PLLM_DIV_14 LL_RCC_PLLM_DIV_15 LL_RCC_PLLM_DIV_16 LL_RCC_PLLM_DIV_17 LL_RCC_PLLM_DIV_18 LL_RCC_PLLM_DIV_19 LL_RCC_PLLM_DIV_20 LL_RCC_PLLM_DIV_21 LL_RCC_PLLM_DIV_22 LL_RCC_PLLM_DIV_23 LL_RCC_PLLM_DIV_24 LL_RCC_PLLM_DIV_25 LL_RCC_PLLM_DIV_26 LL_RCC_PLLM_DIV_27 LL_RCC_PLLM_DIV_28 LL_RCC_PLLM_DIV_29 LL_RCC_PLLM_DIV_30 LL_RCC_PLLM_DIV_31 LL_RCC_PLLM_DIV_32 LL_RCC_PLLM_DIV_33 LL_RCC_PLLM_DIV_34 LL_RCC_PLLM_DIV_35 LL_RCC_PLLM_DIV_36 LL_RCC_PLLM_DIV_37 LL_RCC_PLLM_DIV_38 LL_RCC_PLLM_DIV_39 LL_RCC_PLLM_DIV_40 LL_RCC_PLLM_DIV_41 LL_RCC_PLLM_DIV_42 LL_RCC_PLLM_DIV_43 LL_RCC_PLLM_DIV_44 LL_RCC_PLLM_DIV_45 LL_RCC_PLLM_DIV_46 LL_RCC_PLLM_DIV_47 LL_RCC_PLLM_DIV_48 LL_RCC_PLLM_DIV_49 LL_RCC_PLLM_DIV_50 LL_RCC_PLLM_DIV_51 LL_RCC_PLLM_DIV_52 LL_RCC_PLLM_DIV_53 LL_RCC_PLLM_DIV_54 LL_RCC_PLLM_DIV_55 LL_RCC_PLLM_DIV_56 LL_RCC_PLLM_DIV_57 LL_RCC_PLLM_DIV_58 LL_RCC_PLLM_DIV_59 LL_RCC_PLLM_DIV_60 LL_RCC_PLLM_DIV_61 LL_RCC_PLLM_DIV_62 LL_RCC_PLLM_DIV_63

Definition at line 5044 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_GetDIVR()

__STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR

(

void

)

Get Main PLL division factor for PLLDIVR.

Note

used for PLLSAICLK (SAI1 and SAI2 clock) @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR

Return values

Returned

value can be one of the following values: LL_RCC_PLLDIVR_DIV_1 LL_RCC_PLLDIVR_DIV_2 LL_RCC_PLLDIVR_DIV_3 LL_RCC_PLLDIVR_DIV_4 LL_RCC_PLLDIVR_DIV_5 LL_RCC_PLLDIVR_DIV_6 LL_RCC_PLLDIVR_DIV_7 LL_RCC_PLLDIVR_DIV_8 LL_RCC_PLLDIVR_DIV_9 LL_RCC_PLLDIVR_DIV_10 LL_RCC_PLLDIVR_DIV_11 LL_RCC_PLLDIVR_DIV_12 LL_RCC_PLLDIVR_DIV_13 LL_RCC_PLLDIVR_DIV_14 LL_RCC_PLLDIVR_DIV_15 LL_RCC_PLLDIVR_DIV_16 LL_RCC_PLLDIVR_DIV_17 LL_RCC_PLLDIVR_DIV_18 LL_RCC_PLLDIVR_DIV_19 LL_RCC_PLLDIVR_DIV_20 LL_RCC_PLLDIVR_DIV_21 LL_RCC_PLLDIVR_DIV_22 LL_RCC_PLLDIVR_DIV_23 LL_RCC_PLLDIVR_DIV_24 LL_RCC_PLLDIVR_DIV_25 LL_RCC_PLLDIVR_DIV_26 LL_RCC_PLLDIVR_DIV_27 LL_RCC_PLLDIVR_DIV_28 LL_RCC_PLLDIVR_DIV_29 LL_RCC_PLLDIVR_DIV_30 LL_RCC_PLLDIVR_DIV_31

Definition at line 4971 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_GetMainSource()

__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource

(

void

)

Get the oscillator used as PLL clock source. @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource.

Return values

Returned

value can be one of the following values: LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE

Definition at line 4858 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_GetN()

__STATIC_INLINE uint32_t LL_RCC_PLL_GetN

(

void

)

Get Main PLL multiplication factor for VCO @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN.

Return values

Between

50/192(*) and 432 (*) value not defined in all devices.

Definition at line 4870 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_GetP()

__STATIC_INLINE uint32_t LL_RCC_PLL_GetP

(

void

)

Get Main PLL division factor for PLLP @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP.

Return values

Returned

value can be one of the following values: LL_RCC_PLLP_DIV_2 LL_RCC_PLLP_DIV_4 LL_RCC_PLLP_DIV_6 LL_RCC_PLLP_DIV_8

Definition at line 4884 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_GetPeriodModulation()

__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation

(

void

)

Get Spread Spectrum Modulation Period for PLL @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation.

Return values

Between

Min_Data=0 and Max_Data=8191

Definition at line 5072 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_GetQ()

__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ

(

void

)

Get Main PLL division factor for PLLQ.

Note

used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock) @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ

Return values

Returned

value can be one of the following values: LL_RCC_PLLQ_DIV_2 LL_RCC_PLLQ_DIV_3 LL_RCC_PLLQ_DIV_4 LL_RCC_PLLQ_DIV_5 LL_RCC_PLLQ_DIV_6 LL_RCC_PLLQ_DIV_7 LL_RCC_PLLQ_DIV_8 LL_RCC_PLLQ_DIV_9 LL_RCC_PLLQ_DIV_10 LL_RCC_PLLQ_DIV_11 LL_RCC_PLLQ_DIV_12 LL_RCC_PLLQ_DIV_13 LL_RCC_PLLQ_DIV_14 LL_RCC_PLLQ_DIV_15

Definition at line 4909 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_GetR()

__STATIC_INLINE uint32_t LL_RCC_PLL_GetR

(

void

)

Get Main PLL division factor for PLLR.

Note

used for PLLCLK (system clock) @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR

Return values

Returned

value can be one of the following values: LL_RCC_PLLR_DIV_2 LL_RCC_PLLR_DIV_3 LL_RCC_PLLR_DIV_4 LL_RCC_PLLR_DIV_5 LL_RCC_PLLR_DIV_6 LL_RCC_PLLR_DIV_7

Definition at line 4927 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_GetSpreadSelection()

__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection

(

void

)

Get Spread Spectrum Selection for PLL.

Note

Must be written before enabling PLL @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection

Return values

Returned

value can be one of the following values: LL_RCC_SPREAD_SELECT_CENTER LL_RCC_SPREAD_SELECT_DOWN

Definition at line 5096 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_GetStepIncrementation()

__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation

(

void

)

Get Spread Spectrum Incrementation Step for PLL.

Note

Must be written before enabling PLL @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation

Return values

Between

Min_Data=0 and Max_Data=32767

Definition at line 5083 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_IsReady()

__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady

(

void

)

Check if PLL Ready @rmtoll CR PLLRDY LL_RCC_PLL_IsReady.

Return values

State

of bit (1 or 0).

Definition at line 4206 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_SetMainSource()

__STATIC_INLINE void LL_RCC_PLL_SetMainSource

(

uint32_t

PLLSource

)

Configure PLL clock source @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource.

Parameters

PLLSource

This parameter can be one of the following values: LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE

Return values

None

Definition at line 4846 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_SpreadSpectrum_Disable()

__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable

(

void

)

Disable Spread Spectrum for PLL. @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable.

Return values

None

Definition at line 5116 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLL_SpreadSpectrum_Enable()

__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable

(

void

)

Enable Spread Spectrum for PLL. @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable.

Return values

None

Definition at line 5106 of file stm32f4xx_ll_rcc.h.

Variable Documentation

PLLR

__STATIC_INLINE void uint32_t uint32_t uint32_t PLLR

Initial value:

{
  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR)

Definition at line 4826 of file stm32f4xx_ll_rcc.h.