stm32f4/stm32f4xx__hal__dfsdm_8h_source.html

 /* Define to prevent recursive inclusion -------------------------------------*/

 #ifndef __STM32F4xx_HAL_DFSDM_H

 #define __STM32F4xx_HAL_DFSDM_H


 #ifdef __cplusplus

  extern "C" {

 #endif


 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)

 /* Includes ------------------------------------------------------------------*/

 #include "stm32f4xx_hal_def.h"


 /* Exported types ------------------------------------------------------------*/

 typedef enum

 {

   HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U,

   HAL_DFSDM_CHANNEL_STATE_READY = 0x01U,

   HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU

 }HAL_DFSDM_Channel_StateTypeDef;


 typedef struct

 {

   FunctionalState Activation;

   uint32_t        Selection;

   uint32_t        Divider;

 }DFSDM_Channel_OutputClockTypeDef;


 typedef struct

 {

   uint32_t Multiplexer;

   uint32_t DataPacking;

   uint32_t Pins;

 }DFSDM_Channel_InputTypeDef;


 typedef struct

 {

   uint32_t Type;

   uint32_t SpiClock;

 }DFSDM_Channel_SerialInterfaceTypeDef;


 typedef struct

 {

   uint32_t FilterOrder;

   uint32_t Oversampling;

 }DFSDM_Channel_AwdTypeDef;


 typedef struct

 {

   DFSDM_Channel_OutputClockTypeDef     OutputClock;

   DFSDM_Channel_InputTypeDef           Input;

   DFSDM_Channel_SerialInterfaceTypeDef SerialInterface;

   DFSDM_Channel_AwdTypeDef             Awd;

   int32_t                              Offset;

   uint32_t                             RightBitShift;

 }DFSDM_Channel_InitTypeDef;


 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

 typedef struct __DFSDM_Channel_HandleTypeDef

 #else

 typedef struct

 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */

 {

   DFSDM_Channel_TypeDef          *Instance;

   DFSDM_Channel_InitTypeDef      Init;

   HAL_DFSDM_Channel_StateTypeDef State;

 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

   void (*CkabCallback)      (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

   void (*ScdCallback)       (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

   void (*MspInitCallback)   (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

   void (*MspDeInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

 #endif

 }DFSDM_Channel_HandleTypeDef;


 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

 typedef enum

 {

   HAL_DFSDM_CHANNEL_CKAB_CB_ID      = 0x00U,

   HAL_DFSDM_CHANNEL_SCD_CB_ID       = 0x01U,

   HAL_DFSDM_CHANNEL_MSPINIT_CB_ID   = 0x02U,

   HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U

 }HAL_DFSDM_Channel_CallbackIDTypeDef;


 typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

 #endif

 typedef enum

 {

   HAL_DFSDM_FILTER_STATE_RESET   = 0x00U,

   HAL_DFSDM_FILTER_STATE_READY   = 0x01U,

   HAL_DFSDM_FILTER_STATE_REG     = 0x02U,

   HAL_DFSDM_FILTER_STATE_INJ     = 0x03U,

   HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U,

   HAL_DFSDM_FILTER_STATE_ERROR   = 0xFFU

 }HAL_DFSDM_Filter_StateTypeDef;


 typedef struct

 {

   uint32_t        Trigger;

   FunctionalState FastMode;

   FunctionalState DmaMode;

 }DFSDM_Filter_RegularParamTypeDef;


 typedef struct

 {

   uint32_t        Trigger;

   FunctionalState ScanMode;

   FunctionalState DmaMode;

   uint32_t        ExtTrigger;

   uint32_t        ExtTriggerEdge;

 }DFSDM_Filter_InjectedParamTypeDef;


 typedef struct

 {

   uint32_t SincOrder;

   uint32_t Oversampling;

   uint32_t IntOversampling;

 }DFSDM_Filter_FilterParamTypeDef;


 typedef struct

 {

   DFSDM_Filter_RegularParamTypeDef  RegularParam;

   DFSDM_Filter_InjectedParamTypeDef InjectedParam;

   DFSDM_Filter_FilterParamTypeDef   FilterParam;

 }DFSDM_Filter_InitTypeDef;


 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

 typedef struct __DFSDM_Filter_HandleTypeDef

 #else

 typedef struct

 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */

 {

   DFSDM_Filter_TypeDef          *Instance;

   DFSDM_Filter_InitTypeDef      Init;

   DMA_HandleTypeDef             *hdmaReg;

   DMA_HandleTypeDef             *hdmaInj;

   uint32_t                      RegularContMode;

   uint32_t                      RegularTrigger;

   uint32_t                      InjectedTrigger;

   uint32_t                      ExtTriggerEdge;

   FunctionalState               InjectedScanMode;

   uint32_t                      InjectedChannelsNbr;

   uint32_t                      InjConvRemaining;

   HAL_DFSDM_Filter_StateTypeDef State;

   uint32_t                      ErrorCode;

 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

   void (*AwdCallback)             (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,

                                    uint32_t Channel, uint32_t Threshold);

   void (*RegConvCpltCallback)     (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

   void (*RegConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

   void (*InjConvCpltCallback)     (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

   void (*InjConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

   void (*ErrorCallback)           (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

   void (*MspInitCallback)         (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

   void (*MspDeInitCallback)       (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 #endif

 }DFSDM_Filter_HandleTypeDef;


 typedef struct

 {

   uint32_t DataSource;

   uint32_t Channel;

   int32_t  HighThreshold;

   int32_t  LowThreshold;

   uint32_t HighBreakSignal;

   uint32_t LowBreakSignal;

 }DFSDM_Filter_AwdParamTypeDef;


 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

 typedef enum

 {

   HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID     = 0x00U,

   HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U,

   HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID     = 0x02U,

   HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U,

   HAL_DFSDM_FILTER_ERROR_CB_ID                = 0x04U,

   HAL_DFSDM_FILTER_MSPINIT_CB_ID              = 0x05U,

   HAL_DFSDM_FILTER_MSPDEINIT_CB_ID            = 0x06U

 }HAL_DFSDM_Filter_CallbackIDTypeDef;


 typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);

 #endif


 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)

 typedef struct

 {

   uint32_t  DFSDM1ClockIn;

   uint32_t  DFSDM2ClockIn;

   uint32_t  DFSDM1ClockOut;

   uint32_t  DFSDM2ClockOut;

   uint32_t  DFSDM1BitClkDistribution;

   uint32_t  DFSDM2BitClkDistribution;

   uint32_t  DFSDM1DataDistribution;

   uint32_t  DFSDM2DataDistribution;

 }DFSDM_MultiChannelConfigTypeDef;

 #endif  /* SYSCFG_MCHDLYCR_BSCKSEL */

 /* End of exported types -----------------------------------------------------*/


 /* Exported constants --------------------------------------------------------*/

 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM    0x00000000U

 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO     DFSDM_CHCFGR1_CKOUTSRC

 #define DFSDM_CHANNEL_EXTERNAL_INPUTS        0x00000000U

 #define DFSDM_CHANNEL_INTERNAL_REGISTER      DFSDM_CHCFGR1_DATMPX_1

 #define DFSDM_CHANNEL_STANDARD_MODE          0x00000000U

 #define DFSDM_CHANNEL_INTERLEAVED_MODE       DFSDM_CHCFGR1_DATPACK_0

 #define DFSDM_CHANNEL_DUAL_MODE              DFSDM_CHCFGR1_DATPACK_1

 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS      0x00000000U

 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL

 #define DFSDM_CHANNEL_SPI_RISING             0x00000000U

 #define DFSDM_CHANNEL_SPI_FALLING            DFSDM_CHCFGR1_SITP_0

 #define DFSDM_CHANNEL_MANCHESTER_RISING      DFSDM_CHCFGR1_SITP_1

 #define DFSDM_CHANNEL_MANCHESTER_FALLING     DFSDM_CHCFGR1_SITP

 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL              0x00000000U

 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL              DFSDM_CHCFGR1_SPICKSEL_0

 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1

 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING  DFSDM_CHCFGR1_SPICKSEL

 #define DFSDM_CHANNEL_FASTSINC_ORDER         0x00000000U

 #define DFSDM_CHANNEL_SINC1_ORDER            DFSDM_CHAWSCDR_AWFORD_0

 #define DFSDM_CHANNEL_SINC2_ORDER            DFSDM_CHAWSCDR_AWFORD_1

 #define DFSDM_CHANNEL_SINC3_ORDER            DFSDM_CHAWSCDR_AWFORD

 #define DFSDM_FILTER_SW_TRIGGER              0x00000000U

 #define DFSDM_FILTER_SYNC_TRIGGER            0x00000001U

 #define DFSDM_FILTER_EXT_TRIGGER             0x00000002U

 #if defined(STM32F413xx) || defined(STM32F423xx)

 /* Trigger for stm32f413xx and STM32f423xx devices */

 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  0x00000000U

 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  DFSDM_FLTCR1_JEXTSEL_0

 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1

 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)

 #define DFSDM_FILTER_EXT_TRIG_TIM2_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)

 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  DFSDM_FLTCR1_JEXTSEL_2

 #define DFSDM_FILTER_EXT_TRIG_TIM11_OC1  DFSDM_FLTCR1_JEXTSEL_2

 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)

 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)

 #define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2)

 #define DFSDM_FILTER_EXT_TRIG_EXTI15     DFSDM_FLTCR1_JEXTSEL

 #else

 /* Trigger for stm32f412xx devices */

 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO  0x00000000U

 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO  DFSDM_FLTCR1_JEXTSEL_0

 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO  DFSDM_FLTCR1_JEXTSEL_1

 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1)

 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO  DFSDM_FLTCR1_JEXTSEL_2

 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO  (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)

 #define DFSDM_FILTER_EXT_TRIG_EXTI11     (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2)

 #define DFSDM_FILTER_EXT_TRIG_EXTI15     DFSDM_FLTCR1_JEXTSEL

 #endif

 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE  DFSDM_FLTCR1_JEXTEN_0

 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1

 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES   DFSDM_FLTCR1_JEXTEN

 #define DFSDM_FILTER_FASTSINC_ORDER        0x00000000U

 #define DFSDM_FILTER_SINC1_ORDER           DFSDM_FLTFCR_FORD_0

 #define DFSDM_FILTER_SINC2_ORDER           DFSDM_FLTFCR_FORD_1

 #define DFSDM_FILTER_SINC3_ORDER           (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1)

 #define DFSDM_FILTER_SINC4_ORDER           DFSDM_FLTFCR_FORD_2

 #define DFSDM_FILTER_SINC5_ORDER           (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2)

 #define DFSDM_FILTER_AWD_FILTER_DATA       0x00000000U

 #define DFSDM_FILTER_AWD_CHANNEL_DATA      DFSDM_FLTCR1_AWFSEL

 #define DFSDM_FILTER_ERROR_NONE             0x00000000U

 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN  0x00000001U

 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U

 #define DFSDM_FILTER_ERROR_DMA              0x00000003U

 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

 #define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U

 #endif

 #define DFSDM_NO_BREAK_SIGNAL               0x00000000U

 #define DFSDM_BREAK_SIGNAL_0                0x00000001U

 #define DFSDM_BREAK_SIGNAL_1                0x00000002U

 #define DFSDM_BREAK_SIGNAL_2                0x00000004U

 #define DFSDM_BREAK_SIGNAL_3                0x00000008U

 /* DFSDM Channels ------------------------------------------------------------*/

 /* The DFSDM channels are defined as follows:

    - in 16-bit LSB the channel mask is set

    - in 16-bit MSB the channel number is set

    e.g. for channel 3 definition:

         - the channel mask is 0x00000008 (bit 3 is set)

         - the channel number 3 is 0x00030000

         --> Consequently, channel 3 definition is 0x00000008 | 0x00030000 = 0x00030008 */

 #define DFSDM_CHANNEL_0                     0x00000001U

 #define DFSDM_CHANNEL_1                     0x00010002U

 #define DFSDM_CHANNEL_2                     0x00020004U

 #define DFSDM_CHANNEL_3                     0x00030008U

 #define DFSDM_CHANNEL_4                     0x00040010U            /* only for stmm32f413xx and stm32f423xx devices */

 #define DFSDM_CHANNEL_5                     0x00050020U            /* only for stmm32f413xx and stm32f423xx devices */

 #define DFSDM_CHANNEL_6                     0x00060040U            /* only for stmm32f413xx and stm32f423xx devices */

 #define DFSDM_CHANNEL_7                     0x00070080U            /* only for stmm32f413xx and stm32f423xx devices */

 #define DFSDM_CONTINUOUS_CONV_OFF            0x00000000U

 #define DFSDM_CONTINUOUS_CONV_ON             0x00000001U

 #define DFSDM_AWD_HIGH_THRESHOLD            0x00000000U

 #define DFSDM_AWD_LOW_THRESHOLD             0x00000001U

 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)

 #define DFSDM1_CKOUT_DFSDM2_CKOUT           0x00000080U

 #define DFSDM1_CKOUT_DFSDM1                 0x00000000U

 #define DFSDM2_CKOUT_DFSDM2_CKOUT           0x00040000U

 #define DFSDM2_CKOUT_DFSDM2                 0x00000000U

 #define DFSDM1_CKIN_DFSDM2_CKOUT            0x00000040U

 #define DFSDM1_CKIN_PAD                     0x00000000U

 #define DFSDM2_CKIN_DFSDM2_CKOUT            0x00020000U

 #define DFSDM2_CKIN_PAD                     0x00000000U

 #define DFSDM1_T4_OC2_BITSTREAM_CKIN0       0x00000000U                   /* TIM4_OC2 to CLKIN0 */

 #define DFSDM1_T4_OC2_BITSTREAM_CKIN2       SYSCFG_MCHDLYCR_DFSDM1CK02SEL /* TIM4_OC2 to CLKIN2 */

 #define DFSDM1_T4_OC1_BITSTREAM_CKIN3       SYSCFG_MCHDLYCR_DFSDM1CK13SEL /* TIM4_OC1 to CLKIN3 */

 #define DFSDM1_T4_OC1_BITSTREAM_CKIN1       0x00000000U                   /* TIM4_OC1 to CLKIN1 */

 #define DFSDM2_T3_OC4_BITSTREAM_CKIN0       0x00000000U                   /* TIM3_OC4 to CKIN0 */

 #define DFSDM2_T3_OC4_BITSTREAM_CKIN4       SYSCFG_MCHDLYCR_DFSDM2CK04SEL /* TIM3_OC4 to CKIN4 */

 #define DFSDM2_T3_OC3_BITSTREAM_CKIN5       SYSCFG_MCHDLYCR_DFSDM2CK15SEL /* TIM3_OC3 to CKIN5 */

 #define DFSDM2_T3_OC3_BITSTREAM_CKIN1       0x00000000U                   /* TIM3_OC3 to CKIN1 */

 #define DFSDM2_T3_OC2_BITSTREAM_CKIN6       SYSCFG_MCHDLYCR_DFSDM2CK26SEL /* TIM3_OC2to CKIN6 */

 #define DFSDM2_T3_OC2_BITSTREAM_CKIN2       0x00000000U                   /* TIM3_OC2 to CKIN2 */

 #define DFSDM2_T3_OC1_BITSTREAM_CKIN3       0x00000000U                   /* TIM3_OC1 to CKIN3 */

 #define DFSDM2_T3_OC1_BITSTREAM_CKIN7       SYSCFG_MCHDLYCR_DFSDM2CK37SEL /* TIM3_OC1 to CKIN7 */

 #define DFSDM1_DATIN0_TO_DATIN0_PAD       0x00000000U

 #define DFSDM1_DATIN0_TO_DATIN1_PAD       SYSCFG_MCHDLYCR_DFSDM1D0SEL

 #define DFSDM1_DATIN2_TO_DATIN2_PAD       0x00000000U

 #define DFSDM1_DATIN2_TO_DATIN3_PAD       SYSCFG_MCHDLYCR_DFSDM1D2SEL

 #define DFSDM2_DATIN0_TO_DATIN0_PAD       0x00000000U

 #define DFSDM2_DATIN0_TO_DATIN1_PAD       SYSCFG_MCHDLYCR_DFSDM2D0SEL

 #define DFSDM2_DATIN2_TO_DATIN2_PAD       0x00000000U

 #define DFSDM2_DATIN2_TO_DATIN3_PAD       SYSCFG_MCHDLYCR_DFSDM2D2SEL

 #define DFSDM2_DATIN4_TO_DATIN4_PAD       0x00000000U

 #define DFSDM2_DATIN4_TO_DATIN5_PAD       SYSCFG_MCHDLYCR_DFSDM2D4SEL

 #define DFSDM2_DATIN6_TO_DATIN6_PAD       0x00000000U

 #define DFSDM2_DATIN6_TO_DATIN7_PAD       SYSCFG_MCHDLYCR_DFSDM2D6SEL

 #define HAL_MCHDLY_CLOCK_DFSDM2       SYSCFG_MCHDLYCR_MCHDLY2EN

 #define HAL_MCHDLY_CLOCK_DFSDM1       SYSCFG_MCHDLYCR_MCHDLY1EN

 #define HAL_DFSDM2_CKIN_PAD           0x00040000U

 #define HAL_DFSDM2_CKIN_DM            SYSCFG_MCHDLYCR_DFSDM2CFG

 #define HAL_DFSDM1_CKIN_PAD           0x00000000U

 #define HAL_DFSDM1_CKIN_DM            SYSCFG_MCHDLYCR_DFSDM1CFG

 #define HAL_DFSDM2_CKOUT_DFSDM2       0x10000000U

 #define HAL_DFSDM2_CKOUT_M27          SYSCFG_MCHDLYCR_DFSDM2CKOSEL

 #define HAL_DFSDM1_CKOUT_DFSDM1       0x00000000U

 #define HAL_DFSDM1_CKOUT_M27          SYSCFG_MCHDLYCR_DFSDM1CKOSEL

 #define HAL_DATAIN0_DFSDM2_PAD        0x10000000U

 #define HAL_DATAIN0_DFSDM2_DATAIN1    SYSCFG_MCHDLYCR_DFSDM2D0SEL

 #define HAL_DATAIN0_DFSDM1_PAD        0x00000000U

 #define HAL_DATAIN0_DFSDM1_DATAIN1    SYSCFG_MCHDLYCR_DFSDM1D0SEL

 #define HAL_DATAIN2_DFSDM2_PAD        0x10000000U

 #define HAL_DATAIN2_DFSDM2_DATAIN3    SYSCFG_MCHDLYCR_DFSDM2D2SEL

 #define HAL_DATAIN2_DFSDM1_PAD        0x00000000U

 #define HAL_DATAIN2_DFSDM1_DATAIN3    SYSCFG_MCHDLYCR_DFSDM1D2SEL

 #define HAL_DATAIN4_DFSDM2_PAD        0x00000000U

 #define HAL_DATAIN4_DFSDM2_DATAIN5    SYSCFG_MCHDLYCR_DFSDM2D4SEL

 #define HAL_DATAIN6_DFSDM2_PAD        0x00000000U

 #define HAL_DATAIN6_DFSDM2_DATAIN7    SYSCFG_MCHDLYCR_DFSDM2D6SEL

 #define HAL_DFSDM1_CLKIN0_TIM4OC2      0x01000000U

 #define HAL_DFSDM1_CLKIN2_TIM4OC2      SYSCFG_MCHDLYCR_DFSDM1CK02SEL

 #define HAL_DFSDM1_CLKIN1_TIM4OC1      0x02000000U

 #define HAL_DFSDM1_CLKIN3_TIM4OC1      SYSCFG_MCHDLYCR_DFSDM1CK13SEL

 #define HAL_DFSDM2_CLKIN0_TIM3OC4      0x04000000U

 #define HAL_DFSDM2_CLKIN4_TIM3OC4      SYSCFG_MCHDLYCR_DFSDM2CK04SEL

 #define HAL_DFSDM2_CLKIN1_TIM3OC3      0x08000000U

 #define HAL_DFSDM2_CLKIN5_TIM3OC3      SYSCFG_MCHDLYCR_DFSDM2CK15SEL

 #define HAL_DFSDM2_CLKIN2_TIM3OC2      0x10000000U

 #define HAL_DFSDM2_CLKIN6_TIM3OC2      SYSCFG_MCHDLYCR_DFSDM2CK26SEL

 #define HAL_DFSDM2_CLKIN3_TIM3OC1      0x00000000U

 #define HAL_DFSDM2_CLKIN7_TIM3OC1      SYSCFG_MCHDLYCR_DFSDM2CK37SEL

 #endif /* SYSCFG_MCHDLYCR_BSCKSEL*/

 /* End of exported constants -------------------------------------------------*/


 /* Exported macros -----------------------------------------------------------*/

 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{                                                      \

                                                                (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \

                                                                (__HANDLE__)->MspInitCallback = NULL;                \

                                                                (__HANDLE__)->MspDeInitCallback = NULL;              \

                                                              } while(0)

 #else

 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)

 #endif


 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{                                                     \

                                                               (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \

                                                               (__HANDLE__)->MspInitCallback = NULL;               \

                                                               (__HANDLE__)->MspDeInitCallback = NULL;             \

                                                             } while(0)

 #else

 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)

 #endif


 /* End of exported macros ----------------------------------------------------*/


 /* Exported functions --------------------------------------------------------*/

 /* Channel initialization and de-initialization functions *********************/

 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

 /* Channel callbacks register/unregister functions ****************************/

 HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,

                                                      HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,

                                                      pDFSDM_Channel_CallbackTypeDef      pCallback);

 HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,

                                                        HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID);

 #endif

 /* Channel operation functions ************************************************/

 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);


 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);

 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);

 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);


 int16_t           HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);


 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);

 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);


 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

 /* Channel state function *****************************************************/

 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

 /* Filter initialization and de-initialization functions *********************/

 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

 /* Filter callbacks register/unregister functions ****************************/

 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,

                                                     HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,

                                                     pDFSDM_Filter_CallbackTypeDef      pCallback);

 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,

                                                       HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID);

 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef      *hdfsdm_filter,

                                                        pDFSDM_Filter_AwdCallbackTypeDef pCallback);

 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 #endif

 /* Filter control functions *********************/

 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,

                                                    uint32_t                    Channel,

                                                    uint32_t                    ContinuousMode);

 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,

                                                    uint32_t                    Channel);

 /* Filter operation functions *********************/

 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);

 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);

 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);

 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);

 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,

                                               const DFSDM_Filter_AwdParamTypeDef* awdParam);

 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);

 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);


 int32_t  HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);

 int32_t  HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);

 int32_t  HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);

 int32_t  HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);

 uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);


 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);


 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);

 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);


 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);

 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 /* Filter state functions *****************************************************/

 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 uint32_t                      HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)

 void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct);

 void HAL_DFSDM_BitstreamClock_Start(void);

 void HAL_DFSDM_BitstreamClock_Stop(void);

 void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY);

 void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY);

 void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source);

 void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source);

 void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source);

 void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source);

 void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source);

 void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source);

 void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source);

 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */

 /* End of exported functions -------------------------------------------------*/


 /* Private macros ------------------------------------------------------------*/

 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)          (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \

                                                        ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))

 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))

 #define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \

                                                        ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))

 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE)           (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \

                                                        ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \

                                                        ((MODE) == DFSDM_CHANNEL_DUAL_MODE))

 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS)             (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \

                                                        ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))

 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)  (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \

                                                        ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \

                                                        ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \

                                                        ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))

 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)              (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \

                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \

                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \

                                                        ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))

 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)          (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \

                                                        ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \

                                                        ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \

                                                        ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))

 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO)       ((1U <= (RATIO)) && ((RATIO) <= 32U))

 #define IS_DFSDM_CHANNEL_OFFSET(VALUE)                 ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))

 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE)        ((VALUE) <= 0x1FU)

 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE)          ((VALUE) <= 0xFFU)

 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \

                                                        ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))

 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \

                                                        ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))

 #if defined (STM32F413xx) || defined (STM32F423xx)

 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM2_TRGO) || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM11_OC1) || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11)    || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))

 #define IS_DFSDM_DELAY_CLOCK(CLOCK)                     (((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM2) || \

                                                          ((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM1))

 #else

 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \

                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))

 #endif

 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)           (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \

                                                        ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \

                                                        ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))

 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER)             (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \

                                                        ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \

                                                        ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \

                                                        ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \

                                                        ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \

                                                        ((ORDER) == DFSDM_FILTER_SINC5_ORDER))

 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO)               ((1U <= (RATIO)) && ((RATIO) <= 1024U))

 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO)    ((1U <= (RATIO)) && ((RATIO) <= 256U))

 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)         (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \

                                                        ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))

 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE)           ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))

 #define IS_DFSDM_BREAK_SIGNALS(VALUE)                  ((VALUE) <= 0x0FU)

 #if defined(DFSDM2_Channel0)

 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \

                                                        ((CHANNEL) == DFSDM_CHANNEL_1)  || \

                                                        ((CHANNEL) == DFSDM_CHANNEL_2)  || \

                                                        ((CHANNEL) == DFSDM_CHANNEL_3)  || \

                                                        ((CHANNEL) == DFSDM_CHANNEL_4)  || \

                                                        ((CHANNEL) == DFSDM_CHANNEL_5)  || \

                                                        ((CHANNEL) == DFSDM_CHANNEL_6)  || \

                                                        ((CHANNEL) == DFSDM_CHANNEL_7))

 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))

 #else

 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \

                                                        ((CHANNEL) == DFSDM_CHANNEL_1)  || \

                                                        ((CHANNEL) == DFSDM_CHANNEL_2)  || \

                                                        ((CHANNEL) == DFSDM_CHANNEL_3))

 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU))

 #endif

 #define IS_DFSDM_CONTINUOUS_MODE(MODE)                (((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \

                                                        ((MODE) == DFSDM_CONTINUOUS_CONV_ON))

 #if defined(DFSDM2_Channel0)

 #define IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE)          (((INSTANCE) == DFSDM1_Channel0) || \

                                                        ((INSTANCE) == DFSDM1_Channel1) || \

                                                        ((INSTANCE) == DFSDM1_Channel2) || \

                                                        ((INSTANCE) == DFSDM1_Channel3))

 #define IS_DFSDM1_FILTER_INSTANCE(INSTANCE)          (((INSTANCE) == DFSDM1_Filter0) || \

                                                       ((INSTANCE) == DFSDM1_Filter1))

 #endif /* DFSDM2_Channel0 */


 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)

 #define IS_DFSDM_CLOCKIN_SELECTION(SELECTION)           (((SELECTION) == HAL_DFSDM2_CKIN_PAD) || \

                                                           ((SELECTION) == HAL_DFSDM2_CKIN_DM)  || \

                                                           ((SELECTION) == HAL_DFSDM1_CKIN_PAD) || \

                                                           ((SELECTION) == HAL_DFSDM1_CKIN_DM))

 #define IS_DFSDM_CLOCKOUT_SELECTION(SELECTION)         (((SELECTION) == HAL_DFSDM2_CKOUT_DFSDM2) || \

                                                           ((SELECTION) == HAL_DFSDM2_CKOUT_M27)    || \

                                                           ((SELECTION) == HAL_DFSDM1_CKOUT_DFSDM1) || \

                                                           ((SELECTION) == HAL_DFSDM1_CKOUT_M27))

 #define IS_DFSDM_DATAIN0_SRC_SELECTION(SELECTION)        (((SELECTION) == HAL_DATAIN0_DFSDM2_PAD)    || \

                                                           ((SELECTION) == HAL_DATAIN0_DFSDM2_DATAIN1) || \

                                                           ((SELECTION) == HAL_DATAIN0_DFSDM1_PAD)     || \

                                                           ((SELECTION) == HAL_DATAIN0_DFSDM1_DATAIN1))

 #define IS_DFSDM_DATAIN2_SRC_SELECTION(SELECTION)        (((SELECTION) == HAL_DATAIN2_DFSDM2_PAD)    || \

                                                           ((SELECTION) == HAL_DATAIN2_DFSDM2_DATAIN3) || \

                                                           ((SELECTION) == HAL_DATAIN2_DFSDM1_PAD)     || \

                                                           ((SELECTION) == HAL_DATAIN2_DFSDM1_DATAIN3))

 #define IS_DFSDM_DATAIN4_SRC_SELECTION(SELECTION)        (((SELECTION) == HAL_DATAIN4_DFSDM2_PAD)    || \

                                                           ((SELECTION) == HAL_DATAIN4_DFSDM2_DATAIN5))

 #define IS_DFSDM_DATAIN6_SRC_SELECTION(SELECTION)         (((SELECTION) == HAL_DATAIN6_DFSDM2_PAD)    || \

                                                           ((SELECTION) == HAL_DATAIN6_DFSDM2_DATAIN7))

 #define IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(DISTRIBUTION) (((DISTRIBUTION) == HAL_DFSDM1_CLKIN0_TIM4OC2) || \

                                                           ((DISTRIBUTION) == HAL_DFSDM1_CLKIN2_TIM4OC2) || \

                                                           ((DISTRIBUTION) == HAL_DFSDM1_CLKIN1_TIM4OC1) || \

                                                           ((DISTRIBUTION) == HAL_DFSDM1_CLKIN3_TIM4OC1) || \

                                                           ((DISTRIBUTION) == HAL_DFSDM2_CLKIN0_TIM3OC4) || \

                                                           ((DISTRIBUTION) == HAL_DFSDM2_CLKIN4_TIM3OC4) || \

                                                           ((DISTRIBUTION) == HAL_DFSDM2_CLKIN1_TIM3OC3)|| \

                                                           ((DISTRIBUTION) == HAL_DFSDM2_CLKIN5_TIM3OC3) || \

                                                           ((DISTRIBUTION) == HAL_DFSDM2_CLKIN2_TIM3OC2) || \

                                                           ((DISTRIBUTION) == HAL_DFSDM2_CLKIN6_TIM3OC2) || \

                                                           ((DISTRIBUTION) == HAL_DFSDM2_CLKIN3_TIM3OC1)|| \

                                                           ((DISTRIBUTION) == HAL_DFSDM2_CLKIN7_TIM3OC1))

 #define IS_DFSDM_DFSDM1_CLKOUT(CLKOUT)                 (((CLKOUT) == DFSDM1_CKOUT_DFSDM2_CKOUT)    || \

                                                         ((CLKOUT) == DFSDM1_CKOUT_DFSDM1))

 #define IS_DFSDM_DFSDM2_CLKOUT(CLKOUT)                 (((CLKOUT) == DFSDM2_CKOUT_DFSDM2_CKOUT)    || \

                                                         ((CLKOUT) == DFSDM2_CKOUT_DFSDM2))

 #define IS_DFSDM_DFSDM1_CLKIN(CLKIN)                   (((CLKIN) == DFSDM1_CKIN_DFSDM2_CKOUT)    || \

                                                         ((CLKIN) == DFSDM1_CKIN_PAD))

 #define IS_DFSDM_DFSDM2_CLKIN(CLKIN)                   (((CLKIN) == DFSDM2_CKIN_DFSDM2_CKOUT)    || \

                                                         ((CLKIN) == DFSDM2_CKIN_PAD))

 #define IS_DFSDM_DFSDM1_BIT_CLK(CLK)                   (((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN0)  || \

                                                         ((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN2)  || \

                                                         ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN3)  || \

                                                         ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN1)  || \

                                                         ((CLK) <= 0x30U))


 #define IS_DFSDM_DFSDM2_BIT_CLK(CLK)                   (((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN0)  || \

                                                         ((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN4)  || \

                                                         ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN5)  || \

                                                         ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN1)  || \

                                                         ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN6)  || \

                                                         ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN2)  || \

                                                         ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN3)  || \

                                                         ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN7)|| \

                                                         ((CLK) <= 0x1E000U))


 #define IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN0_PAD )|| \

                                                         ((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN1_PAD) || \

                                                         ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN2_PAD) || \

                                                         ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN3_PAD)|| \

                                                         ((DISTRIBUTION) <= 0xCU))


 #define IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN0_PAD)|| \

                                                         ((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN1_PAD)|| \

                                                         ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN2_PAD)|| \

                                                         ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN3_PAD)|| \

                                                         ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN4_PAD)|| \

                                                         ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN5_PAD)|| \

                                                         ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN6_PAD)|| \

                                                         ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN7_PAD)|| \

                                                         ((DISTRIBUTION) <= 0x1D00U))

 #endif /* (SYSCFG_MCHDLYCR_BSCKSEL) */

 /* End of private macros -----------------------------------------------------*/


 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */

 #ifdef __cplusplus

 }

 #endif


 #endif /* __STM32F4xx_HAL_DFSDM_H */

endif::InjectedChannelsNbr
uint32_t InjectedChannelsNbr
Definition: stm32f4xx_hal_dfsdm.h:233

endif::State
HAL_DFSDM_Channel_StateTypeDef State
Definition: stm32f4xx_hal_dfsdm.h:127

endif::InjectedScanMode
FunctionalState InjectedScanMode
Definition: stm32f4xx_hal_dfsdm.h:232

endif::Init
DFSDM_Channel_InitTypeDef Init
Definition: stm32f4xx_hal_dfsdm.h:126

endif::InjConvRemaining
uint32_t InjConvRemaining
Definition: stm32f4xx_hal_dfsdm.h:234

endif::Instance
DFSDM_Filter_TypeDef * Instance
Definition: stm32f4xx_hal_dfsdm.h:224

endif::ExtTriggerEdge
uint32_t ExtTriggerEdge
Definition: stm32f4xx_hal_dfsdm.h:231

endif::RegularTrigger
uint32_t RegularTrigger
Definition: stm32f4xx_hal_dfsdm.h:229

endif::InjectedTrigger
uint32_t InjectedTrigger
Definition: stm32f4xx_hal_dfsdm.h:230

endif::Init
DFSDM_Filter_InitTypeDef Init
Definition: stm32f4xx_hal_dfsdm.h:225

endif::hdmaInj
DMA_HandleTypeDef * hdmaInj
Definition: stm32f4xx_hal_dfsdm.h:227

endif::hdmaReg
DMA_HandleTypeDef * hdmaReg
Definition: stm32f4xx_hal_dfsdm.h:226

endif::RegularContMode
uint32_t RegularContMode
Definition: stm32f4xx_hal_dfsdm.h:228

endif::State
HAL_DFSDM_Filter_StateTypeDef State
Definition: stm32f4xx_hal_dfsdm.h:235

endif::Instance
DFSDM_Channel_TypeDef * Instance
Definition: stm32f4xx_hal_dfsdm.h:125

endif
ADC handle Structure definition.
Definition: stm32f4xx_hal_adc.h:197

HAL_DFSDM_ChannelDeInit
HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel.
Definition: stm32f4xx_hal_dfsdm.c:575

HAL_DFSDM_Channel_RegisterCallback
HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, pDFSDM_Channel_CallbackTypeDef pCallback)
Register a user DFSDM channel callback to be used instead of the weak predefined callback.
Definition: stm32f4xx_hal_dfsdm.c:723

HAL_DFSDM_Channel_UnRegisterCallback
HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID)
Unregister a user DFSDM channel callback. DFSDM channel callback is redirected to the weak predefined...
Definition: stm32f4xx_hal_dfsdm.c:795

HAL_DFSDM_ChannelMspDeInit
void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel MSP.
Definition: stm32f4xx_hal_dfsdm.c:700

HAL_DFSDM_ChannelMspInit
void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel MSP.
Definition: stm32f4xx_hal_dfsdm.c:686

HAL_DFSDM_ChannelInit
HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel according to the specified parameters in the DFSDM_ChannelInitTypeDef st...
Definition: stm32f4xx_hal_dfsdm.c:367

HAL_DFSDM_FilterMspInit
void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initializes the DFSDM filter MSP.
Definition: stm32f4xx_hal_dfsdm.c:1859

HAL_DFSDM_Filter_RegisterAwdCallback
HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, pDFSDM_Filter_AwdCallbackTypeDef pCallback)
Register a user DFSDM filter analog watchdog callback to be used instead of the weak predefined callb...
Definition: stm32f4xx_hal_dfsdm.c:2064

HAL_DFSDM_Filter_UnRegisterCallback
HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID)
Unregister a user DFSDM filter callback. DFSDM filter callback is redirected to the weak predefined c...
Definition: stm32f4xx_hal_dfsdm.c:1991

HAL_DFSDM_FilterMspDeInit
void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter MSP.
Definition: stm32f4xx_hal_dfsdm.c:1873

HAL_DFSDM_Filter_RegisterCallback
HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, pDFSDM_Filter_CallbackTypeDef pCallback)
Register a user DFSDM filter callback to be used instead of the weak predefined callback.
Definition: stm32f4xx_hal_dfsdm.c:1899

HAL_DFSDM_FilterInit
HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initialize the DFSDM filter according to the specified parameters in the DFSDM_FilterInitTypeDef stru...
Definition: stm32f4xx_hal_dfsdm.c:1688

HAL_DFSDM_FilterDeInit
HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter.
Definition: stm32f4xx_hal_dfsdm.c:1823

HAL_DFSDM_Filter_UnRegisterAwdCallback
HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Unregister a user DFSDM filter analog watchdog callback. DFSDM filter AWD callback is redirected to t...
Definition: stm32f4xx_hal_dfsdm.c:2099

HAL_DFSDM_ChannelScdStart
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in polling mode.
Definition: stm32f4xx_hal_dfsdm.c:1295

HAL_DFSDM_ChannelScdStart_IT
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:1473

HAL_DFSDM_ChannelCkabStart
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in polling mode.
Definition: stm32f4xx_hal_dfsdm.c:875

HAL_DFSDM_ChannelCkabCallback
void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Clock absence detection callback.
Definition: stm32f4xx_hal_dfsdm.c:1212

HAL_DFSDM_ChannelCkabStop_IT
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:1227

HAL_DFSDM_ChannelGetAwdValue
int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get channel analog watchdog value.
Definition: stm32f4xx_hal_dfsdm.c:1599

HAL_DFSDM_ChannelPollForScd
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the short circuit detection.
Definition: stm32f4xx_hal_dfsdm.c:1332

HAL_DFSDM_ChannelScdStop
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in polling mode.
Definition: stm32f4xx_hal_dfsdm.c:1418

HAL_DFSDM_ChannelPollForCkab
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the clock absence detection.
Definition: stm32f4xx_hal_dfsdm.c:963

HAL_DFSDM_ChannelModifyOffset
HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset)
This function allows to modify channel offset value.
Definition: stm32f4xx_hal_dfsdm.c:1611

HAL_DFSDM_ChannelScdCallback
void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Short circuit detection callback.
Definition: stm32f4xx_hal_dfsdm.c:1529

HAL_DFSDM_ChannelCkabStart_IT
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:1111

HAL_DFSDM_ChannelCkabStop
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in polling mode.
Definition: stm32f4xx_hal_dfsdm.c:1051

HAL_DFSDM_ChannelScdStop_IT
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:1544

HAL_DFSDM_FilterConfigRegChannel
HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channel and to enable/disable continuous mode for regular conversion.
Definition: stm32f4xx_hal_dfsdm.c:2145

HAL_DFSDM_FilterConfigInjChannel
HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to select channels for injected conversion.
Definition: stm32f4xx_hal_dfsdm.c:2190

HAL_DFSDM_ChannelGetState
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get the current DFSDM channel handle state.
Definition: stm32f4xx_hal_dfsdm.c:1658

HAL_DFSDM_FilterRegConvCpltCallback
void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Regular conversion complete callback.
Definition: stm32f4xx_hal_dfsdm.c:3569

HAL_DFSDM_FilterRegularStart
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in polling mode.
Definition: stm32f4xx_hal_dfsdm.c:2260

HAL_DFSDM_FilterGetInjectedValue
int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get injected conversion value.
Definition: stm32f4xx_hal_dfsdm.c:3054

HAL_DFSDM_FilterRegularStop_IT
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:2415

HAL_DFSDM_FilterInjectedStart_DMA
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode.
Definition: stm32f4xx_hal_dfsdm.c:2871

HAL_DFSDM_IRQHandler
void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function handles the DFSDM interrupts.
Definition: stm32f4xx_hal_dfsdm.c:3317

HAL_DFSDM_FilterInjConvCpltCallback
void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Injected conversion complete callback.
Definition: stm32f4xx_hal_dfsdm.c:3599

HAL_DFSDM_FilterGetExdMinValue
int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector minimum value.
Definition: stm32f4xx_hal_dfsdm.c:3267

HAL_DFSDM_FilterExdStop
HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop extreme detector feature.
Definition: stm32f4xx_hal_dfsdm.c:3201

HAL_DFSDM_FilterAwdCallback
void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold)
Filter analog watchdog callback.
Definition: stm32f4xx_hal_dfsdm.c:3629

HAL_DFSDM_FilterRegularMsbStart_DMA
HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode and to get only the 16 most significant ...
Definition: stm32f4xx_hal_dfsdm.c:2530

HAL_DFSDM_FilterPollForRegConversion
HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of regular conversion.
Definition: stm32f4xx_hal_dfsdm.c:2289

HAL_DFSDM_FilterInjectedMsbStart_DMA
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode and to get only the 16 most significant...
Definition: stm32f4xx_hal_dfsdm.c:2946

HAL_DFSDM_FilterAwdStop_IT
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop filter analog watchdog in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:3130

HAL_DFSDM_FilterRegularStart_DMA
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode.
Definition: stm32f4xx_hal_dfsdm.c:2453

HAL_DFSDM_FilterGetExdMaxValue
int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector maximum value.
Definition: stm32f4xx_hal_dfsdm.c:3239

HAL_DFSDM_FilterErrorCallback
void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Error callback.
Definition: stm32f4xx_hal_dfsdm.c:3647

HAL_DFSDM_FilterInjectedStop_DMA
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in DMA mode.
Definition: stm32f4xx_hal_dfsdm.c:3015

HAL_DFSDM_FilterRegularStop
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in polling mode.
Definition: stm32f4xx_hal_dfsdm.c:2354

HAL_DFSDM_FilterRegularStop_DMA
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in DMA mode.
Definition: stm32f4xx_hal_dfsdm.c:2601

HAL_DFSDM_FilterPollForInjConversion
HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of injected conversion.
Definition: stm32f4xx_hal_dfsdm.c:2697

HAL_DFSDM_FilterInjectedStart_IT
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:2802

HAL_DFSDM_FilterInjectedStart
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in polling mode.
Definition: stm32f4xx_hal_dfsdm.c:2668

HAL_DFSDM_FilterInjectedStop_IT
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:2833

HAL_DFSDM_FilterExdStart
HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to start extreme detector feature.
Definition: stm32f4xx_hal_dfsdm.c:3170

HAL_DFSDM_FilterGetRegularValue
int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get regular conversion value.
Definition: stm32f4xx_hal_dfsdm.c:2640

HAL_DFSDM_FilterInjectedStop
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in polling mode.
Definition: stm32f4xx_hal_dfsdm.c:2772

HAL_DFSDM_FilterRegConvHalfCpltCallback
void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half regular conversion complete callback.
Definition: stm32f4xx_hal_dfsdm.c:3583

HAL_DFSDM_FilterGetConvTimeValue
uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get conversion time value.
Definition: stm32f4xx_hal_dfsdm.c:3294

HAL_DFSDM_FilterAwdStart_IT
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, const DFSDM_Filter_AwdParamTypeDef *awdParam)
This function allows to start filter analog watchdog in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:3081

HAL_DFSDM_FilterRegularStart_IT
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:2384

HAL_DFSDM_FilterInjConvHalfCpltCallback
void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half injected conversion complete callback.
Definition: stm32f4xx_hal_dfsdm.c:3613

HAL_DFSDM_FilterGetState
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter handle state.
Definition: stm32f4xx_hal_dfsdm.c:3679

HAL_DFSDM_FilterGetError
uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter error.
Definition: stm32f4xx_hal_dfsdm.c:3690

HAL_DFSDM_BitStreamClkDistribution_Config
void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source)
Configure the distribution of the bitstream clock gated from TIM4_OC for DFSDM1 or TIM3_OC for DFSDM2...
Definition: stm32f4xx_hal_dfsdm.c:3972

HAL_DFSDM_DataIn2_SourceSelection
void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source)
Select the source for DataIn2 signals for DFSDM1/2.
Definition: stm32f4xx_hal_dfsdm.c:3895

HAL_DFSDM_ClockOut_SourceSelection
void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source)
Select the source for CKOut signals for DFSDM1/2.
Definition: stm32f4xx_hal_dfsdm.c:3831

HAL_DFSDM_BitstreamClock_Start
void HAL_DFSDM_BitstreamClock_Start(void)
Select the DFSDM2 as clock source for the bitstream clock.
Definition: stm32f4xx_hal_dfsdm.c:3717

HAL_DFSDM_ClockIn_SourceSelection
void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source)
Select the source for CKin signals for DFSDM1/2.
Definition: stm32f4xx_hal_dfsdm.c:3798

HAL_DFSDM_EnableDelayClock
void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY)
Enable Delay Clock for DFSDM1/2.
Definition: stm32f4xx_hal_dfsdm.c:3778

HAL_DFSDM_DataIn0_SourceSelection
void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source)
Select the source for DataIn0 signals for DFSDM1/2.
Definition: stm32f4xx_hal_dfsdm.c:3864

HAL_DFSDM_DataIn4_SourceSelection
void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source)
Select the source for DataIn4 signals for DFSDM2.
Definition: stm32f4xx_hal_dfsdm.c:3924

HAL_DFSDM_DataIn6_SourceSelection
void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source)
Select the source for DataIn6 signals for DFSDM2.
Definition: stm32f4xx_hal_dfsdm.c:3942

HAL_DFSDM_ConfigMultiChannelDelay
void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef *mchdlystruct)
Configure multi channel delay block: Use DFSDM2 audio clock source as input clock for DFSDM1 and DFSD...
Definition: stm32f4xx_hal_dfsdm.c:4030

HAL_DFSDM_BitstreamClock_Stop
void HAL_DFSDM_BitstreamClock_Stop(void)
Stop the DFSDM2 as clock source for the bitstream clock.
Definition: stm32f4xx_hal_dfsdm.c:3733

HAL_DFSDM_DisableDelayClock
void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY)
Disable Delay Clock for DFSDM1/2.
Definition: stm32f4xx_hal_dfsdm.c:3751

stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.

DFSDM_Filter_FilterParamTypeDef::IntOversampling
uint32_t IntOversampling
Definition: stm32f4xx_hal_dfsdm.h:201

DFSDM_Filter_AwdParamTypeDef::LowThreshold
int32_t LowThreshold
Definition: stm32f4xx_hal_dfsdm.h:261

DFSDM_Channel_InitTypeDef::Offset
int32_t Offset
Definition: stm32f4xx_hal_dfsdm.h:110

DFSDM_MultiChannelConfigTypeDef::DFSDM2DataDistribution
uint32_t DFSDM2DataDistribution
Definition: stm32f4xx_hal_dfsdm.h:320

DFSDM_Filter_RegularParamTypeDef::FastMode
FunctionalState FastMode
Definition: stm32f4xx_hal_dfsdm.h:173

DFSDM_Channel_AwdTypeDef::FilterOrder
uint32_t FilterOrder
Definition: stm32f4xx_hal_dfsdm.h:95

DFSDM_Channel_OutputClockTypeDef::Activation
FunctionalState Activation
Definition: stm32f4xx_hal_dfsdm.h:59

DFSDM_Filter_InjectedParamTypeDef::ScanMode
FunctionalState ScanMode
Definition: stm32f4xx_hal_dfsdm.h:184

HAL_DFSDM_Filter_CallbackIDTypeDef
HAL_DFSDM_Filter_CallbackIDTypeDef
DFSDM filter callback ID enumeration definition.
Definition: stm32f4xx_hal_dfsdm.h:274

HAL_DFSDM_FILTER_MSPINIT_CB_ID
@ HAL_DFSDM_FILTER_MSPINIT_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:280

HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID
@ HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:278

HAL_DFSDM_FILTER_MSPDEINIT_CB_ID
@ HAL_DFSDM_FILTER_MSPDEINIT_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:281

HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID
@ HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:276

HAL_DFSDM_FILTER_ERROR_CB_ID
@ HAL_DFSDM_FILTER_ERROR_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:279

HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID
@ HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:275

HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID
@ HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:277

DFSDM_Filter_RegularParamTypeDef::Trigger
uint32_t Trigger
Definition: stm32f4xx_hal_dfsdm.h:171

DFSDM_Channel_HandleTypeDef
struct __DFSDM_Channel_HandleTypeDef else typedef struct endif DFSDM_Channel_HandleTypeDef
DFSDM channel handle structure definition.

DFSDM_Channel_InputTypeDef::Pins
uint32_t Pins
Definition: stm32f4xx_hal_dfsdm.h:75

DFSDM_Filter_AwdParamTypeDef::HighBreakSignal
uint32_t HighBreakSignal
Definition: stm32f4xx_hal_dfsdm.h:263

DFSDM_Filter_FilterParamTypeDef::Oversampling
uint32_t Oversampling
Definition: stm32f4xx_hal_dfsdm.h:199

DFSDM_Channel_AwdTypeDef::Oversampling
uint32_t Oversampling
Definition: stm32f4xx_hal_dfsdm.h:97

DFSDM_Filter_FilterParamTypeDef::SincOrder
uint32_t SincOrder
Definition: stm32f4xx_hal_dfsdm.h:197

DFSDM_Filter_RegularParamTypeDef::DmaMode
FunctionalState DmaMode
Definition: stm32f4xx_hal_dfsdm.h:174

DFSDM_Channel_InputTypeDef::DataPacking
uint32_t DataPacking
Definition: stm32f4xx_hal_dfsdm.h:73

DFSDM_Filter_InitTypeDef::RegularParam
DFSDM_Filter_RegularParamTypeDef RegularParam
Definition: stm32f4xx_hal_dfsdm.h:210

DFSDM_Channel_InitTypeDef::SerialInterface
DFSDM_Channel_SerialInterfaceTypeDef SerialInterface
Definition: stm32f4xx_hal_dfsdm.h:108

DFSDM_Filter_AwdParamTypeDef::HighThreshold
int32_t HighThreshold
Definition: stm32f4xx_hal_dfsdm.h:259

DFSDM_MultiChannelConfigTypeDef::DFSDM1BitClkDistribution
uint32_t DFSDM1BitClkDistribution
Definition: stm32f4xx_hal_dfsdm.h:308

DFSDM_Channel_OutputClockTypeDef::Selection
uint32_t Selection
Definition: stm32f4xx_hal_dfsdm.h:60

DFSDM_Filter_InjectedParamTypeDef::DmaMode
FunctionalState DmaMode
Definition: stm32f4xx_hal_dfsdm.h:185

DFSDM_Channel_InitTypeDef::Input
DFSDM_Channel_InputTypeDef Input
Definition: stm32f4xx_hal_dfsdm.h:107

DFSDM_Channel_InitTypeDef::RightBitShift
uint32_t RightBitShift
Definition: stm32f4xx_hal_dfsdm.h:112

pDFSDM_Channel_CallbackTypeDef
void(* pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
DFSDM channel callback pointer definition.
Definition: stm32f4xx_hal_dfsdm.h:151

DFSDM_MultiChannelConfigTypeDef::DFSDM2ClockIn
uint32_t DFSDM2ClockIn
Definition: stm32f4xx_hal_dfsdm.h:302

HAL_DFSDM_Filter_StateTypeDef
HAL_DFSDM_Filter_StateTypeDef
HAL DFSDM Filter states definition.
Definition: stm32f4xx_hal_dfsdm.h:157

HAL_DFSDM_FILTER_STATE_INJ
@ HAL_DFSDM_FILTER_STATE_INJ
Definition: stm32f4xx_hal_dfsdm.h:161

HAL_DFSDM_FILTER_STATE_ERROR
@ HAL_DFSDM_FILTER_STATE_ERROR
Definition: stm32f4xx_hal_dfsdm.h:163

HAL_DFSDM_FILTER_STATE_REG
@ HAL_DFSDM_FILTER_STATE_REG
Definition: stm32f4xx_hal_dfsdm.h:160

HAL_DFSDM_FILTER_STATE_REG_INJ
@ HAL_DFSDM_FILTER_STATE_REG_INJ
Definition: stm32f4xx_hal_dfsdm.h:162

HAL_DFSDM_FILTER_STATE_READY
@ HAL_DFSDM_FILTER_STATE_READY
Definition: stm32f4xx_hal_dfsdm.h:159

HAL_DFSDM_FILTER_STATE_RESET
@ HAL_DFSDM_FILTER_STATE_RESET
Definition: stm32f4xx_hal_dfsdm.h:158

pDFSDM_Filter_CallbackTypeDef
void(* pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
DFSDM filter callback pointer definition.
Definition: stm32f4xx_hal_dfsdm.h:287

DFSDM_Filter_InjectedParamTypeDef::ExtTriggerEdge
uint32_t ExtTriggerEdge
Definition: stm32f4xx_hal_dfsdm.h:188

DFSDM_Filter_InitTypeDef::InjectedParam
DFSDM_Filter_InjectedParamTypeDef InjectedParam
Definition: stm32f4xx_hal_dfsdm.h:211

DFSDM_Filter_AwdParamTypeDef::LowBreakSignal
uint32_t LowBreakSignal
Definition: stm32f4xx_hal_dfsdm.h:265

DFSDM_MultiChannelConfigTypeDef::DFSDM2ClockOut
uint32_t DFSDM2ClockOut
Definition: stm32f4xx_hal_dfsdm.h:306

DFSDM_Channel_SerialInterfaceTypeDef::SpiClock
uint32_t SpiClock
Definition: stm32f4xx_hal_dfsdm.h:86

DFSDM_MultiChannelConfigTypeDef::DFSDM1ClockIn
uint32_t DFSDM1ClockIn
Definition: stm32f4xx_hal_dfsdm.h:300

HAL_DFSDM_Channel_CallbackIDTypeDef
HAL_DFSDM_Channel_CallbackIDTypeDef
DFSDM channel callback ID enumeration definition.
Definition: stm32f4xx_hal_dfsdm.h:141

HAL_DFSDM_CHANNEL_SCD_CB_ID
@ HAL_DFSDM_CHANNEL_SCD_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:143

HAL_DFSDM_CHANNEL_CKAB_CB_ID
@ HAL_DFSDM_CHANNEL_CKAB_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:142

HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID
@ HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:145

HAL_DFSDM_CHANNEL_MSPINIT_CB_ID
@ HAL_DFSDM_CHANNEL_MSPINIT_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:144

DFSDM_Filter_InjectedParamTypeDef::Trigger
uint32_t Trigger
Definition: stm32f4xx_hal_dfsdm.h:182

DFSDM_MultiChannelConfigTypeDef::DFSDM1DataDistribution
uint32_t DFSDM1DataDistribution
Definition: stm32f4xx_hal_dfsdm.h:318

DFSDM_Channel_SerialInterfaceTypeDef::Type
uint32_t Type
Definition: stm32f4xx_hal_dfsdm.h:84

DFSDM_Channel_InitTypeDef::Awd
DFSDM_Channel_AwdTypeDef Awd
Definition: stm32f4xx_hal_dfsdm.h:109

DFSDM_Filter_HandleTypeDef
struct __DFSDM_Filter_HandleTypeDef else typedef struct endif DFSDM_Filter_HandleTypeDef
DFSDM filter handle structure definition.

DFSDM_Channel_InputTypeDef::Multiplexer
uint32_t Multiplexer
Definition: stm32f4xx_hal_dfsdm.h:71

DFSDM_Filter_InitTypeDef::FilterParam
DFSDM_Filter_FilterParamTypeDef FilterParam
Definition: stm32f4xx_hal_dfsdm.h:212

DFSDM_MultiChannelConfigTypeDef::DFSDM1ClockOut
uint32_t DFSDM1ClockOut
Definition: stm32f4xx_hal_dfsdm.h:304

DFSDM_Filter_AwdParamTypeDef::Channel
uint32_t Channel
Definition: stm32f4xx_hal_dfsdm.h:257

DFSDM_Channel_InitTypeDef::OutputClock
DFSDM_Channel_OutputClockTypeDef OutputClock
Definition: stm32f4xx_hal_dfsdm.h:106

DFSDM_Filter_InjectedParamTypeDef::ExtTrigger
uint32_t ExtTrigger
Definition: stm32f4xx_hal_dfsdm.h:186

DFSDM_Channel_OutputClockTypeDef::Divider
uint32_t Divider
Definition: stm32f4xx_hal_dfsdm.h:62

DFSDM_MultiChannelConfigTypeDef::DFSDM2BitClkDistribution
uint32_t DFSDM2BitClkDistribution
Definition: stm32f4xx_hal_dfsdm.h:312

DFSDM_Filter_AwdParamTypeDef::DataSource
uint32_t DataSource
Definition: stm32f4xx_hal_dfsdm.h:255

DFSDM_Channel_AwdTypeDef
DFSDM channel analog watchdog structure definition.
Definition: stm32f4xx_hal_dfsdm.h:94

DFSDM_Channel_InitTypeDef
DFSDM channel init structure definition.
Definition: stm32f4xx_hal_dfsdm.h:105

DFSDM_Channel_InputTypeDef
DFSDM channel input structure definition.
Definition: stm32f4xx_hal_dfsdm.h:70

DFSDM_Channel_OutputClockTypeDef
DFSDM channel output clock structure definition.
Definition: stm32f4xx_hal_dfsdm.h:58

DFSDM_Channel_SerialInterfaceTypeDef
DFSDM channel serial interface structure definition.
Definition: stm32f4xx_hal_dfsdm.h:83

DFSDM_Filter_AwdParamTypeDef
DFSDM filter analog watchdog parameters structure definition.
Definition: stm32f4xx_hal_dfsdm.h:254

DFSDM_Filter_FilterParamTypeDef
DFSDM filter parameters structure definition.
Definition: stm32f4xx_hal_dfsdm.h:196

DFSDM_Filter_InitTypeDef
DFSDM filter init structure definition.
Definition: stm32f4xx_hal_dfsdm.h:209

DFSDM_Filter_InjectedParamTypeDef
DFSDM filter injected conversion parameters structure definition.
Definition: stm32f4xx_hal_dfsdm.h:181

DFSDM_Filter_RegularParamTypeDef
DFSDM filter regular conversion parameters structure definition.
Definition: stm32f4xx_hal_dfsdm.h:170

DFSDM_MultiChannelConfigTypeDef
Synchronization parameters structure definition for STM32F413xx/STM32F423xx devices.
Definition: stm32f4xx_hal_dfsdm.h:299

__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f4xx_hal_dma.h:139