STM32F4xx_HAL_Driver  1.8.3
stm32f4xx_hal_dfsdm.c
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1 
267 /* Includes ------------------------------------------------------------------*/
268 #include "stm32f4xx_hal.h"
269 
273 #ifdef HAL_DFSDM_MODULE_ENABLED
274 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
280 /* Private typedef -----------------------------------------------------------*/
281 /* Private define ------------------------------------------------------------*/
286 #define DFSDM_FLTCR1_MSB_RCH_OFFSET 8U
287 
288 #define DFSDM_MSB_MASK 0xFFFF0000U
289 #define DFSDM_LSB_MASK 0x0000FFFFU
290 #define DFSDM_CKAB_TIMEOUT 5000U
291 #define DFSDM1_CHANNEL_NUMBER 4U
292 #if defined (DFSDM2_Channel0)
293 #define DFSDM2_CHANNEL_NUMBER 8U
294 #endif /* DFSDM2_Channel0 */
295 
306 /* Private macro -------------------------------------------------------------*/
307 /* Private variables ---------------------------------------------------------*/
311 __IO uint32_t v_dfsdm1ChannelCounter = 0U;
312 DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};
313 
314 #if defined (DFSDM2_Channel0)
315 __IO uint32_t v_dfsdm2ChannelCounter = 0U;
316 DFSDM_Channel_HandleTypeDef* a_dfsdm2ChannelHandle[DFSDM2_CHANNEL_NUMBER] = {NULL};
317 #endif /* DFSDM2_Channel0 */
322 /* Private function prototypes -----------------------------------------------*/
326 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);
327 static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance);
328 static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
329 static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
330 static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
331 static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
332 static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
333 static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
334 static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
335 static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
336 static void DFSDM_DMAError(DMA_HandleTypeDef *hdma);
337 
342 /* Exported functions --------------------------------------------------------*/
367 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
368 {
369 #if defined(DFSDM2_Channel0)
370  __IO uint32_t* channelCounterPtr;
371  DFSDM_Channel_HandleTypeDef **channelHandleTable;
372  DFSDM_Channel_TypeDef* channel0Instance;
373 #endif /* defined(DFSDM2_Channel0) */
374 
375  /* Check DFSDM Channel handle */
376  if(hdfsdm_channel == NULL)
377  {
378  return HAL_ERROR;
379  }
380 
381  /* Check parameters */
382  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
383  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));
384  assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));
385  assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));
386  assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));
387  assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));
388  assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));
389  assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));
390  assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
391  assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
392  assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
393 
394 #if defined(DFSDM2_Channel0)
395  /* Get channel counter, channel handle table and channel 0 instance */
396  if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
397  {
398  channelCounterPtr = &v_dfsdm1ChannelCounter;
399  channelHandleTable = a_dfsdm1ChannelHandle;
400  channel0Instance = DFSDM1_Channel0;
401  }
402  else
403  {
404  channelCounterPtr = &v_dfsdm2ChannelCounter;
405  channelHandleTable = a_dfsdm2ChannelHandle;
406  channel0Instance = DFSDM2_Channel0;
407  }
408 
409  /* Check that channel has not been already initialized */
410  if(channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
411  {
412  return HAL_ERROR;
413  }
414 
415 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
416  /* Reset callback pointers to the weak predefined callbacks */
417  hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
418  hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
419 
420  /* Call MSP init function */
421  if(hdfsdm_channel->MspInitCallback == NULL)
422  {
423  hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
424  }
425  hdfsdm_channel->MspInitCallback(hdfsdm_channel);
426 #else
427  /* Call MSP init function */
428  HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
429 #endif
430 
431  /* Update the channel counter */
432  (*channelCounterPtr)++;
433 
434  /* Configure output serial clock and enable global DFSDM interface only for first channel */
435  if(*channelCounterPtr == 1U)
436  {
437  assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
438  /* Set the output serial clock source */
439  channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
440  channel0Instance->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
441 
442  /* Reset clock divider */
443  channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
444  if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
445  {
446  assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
447  /* Set the output clock divider */
448  channel0Instance->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
449  DFSDM_CHCFGR1_CKOUTDIV_Pos);
450  }
451 
452  /* enable the DFSDM global interface */
453  channel0Instance->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
454  }
455 
456  /* Set channel input parameters */
457  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
458  DFSDM_CHCFGR1_CHINSEL);
459  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
460  hdfsdm_channel->Init.Input.DataPacking |
461  hdfsdm_channel->Init.Input.Pins);
462 
463  /* Set serial interface parameters */
464  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
465  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
466  hdfsdm_channel->Init.SerialInterface.SpiClock);
467 
468  /* Set analog watchdog parameters */
469  hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
470  hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
471  ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
472 
473  /* Set channel offset and right bit shift */
474  hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
475  hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
476  (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
477 
478  /* Enable DFSDM channel */
479  hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
480 
481  /* Set DFSDM Channel to ready state */
482  hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
483 
484  /* Store channel handle in DFSDM channel handle table */
485  channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
486 
487 #else
488  /* Check that channel has not been already initialized */
489  if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
490  {
491  return HAL_ERROR;
492  }
493 
494 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
495  /* Reset callback pointers to the weak predefined callbacks */
496  hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
497  hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
498 
499  /* Call MSP init function */
500  if(hdfsdm_channel->MspInitCallback == NULL)
501  {
502  hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
503  }
504  hdfsdm_channel->MspInitCallback(hdfsdm_channel);
505 #else
506  /* Call MSP init function */
507  HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
508 #endif
509 
510  /* Update the channel counter */
511  v_dfsdm1ChannelCounter++;
512 
513  /* Configure output serial clock and enable global DFSDM interface only for first channel */
514  if(v_dfsdm1ChannelCounter == 1U)
515  {
516  assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
517  /* Set the output serial clock source */
518  DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
519  DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
520 
521  /* Reset clock divider */
522  DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
523  if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
524  {
525  assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
526  /* Set the output clock divider */
527  DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
528  DFSDM_CHCFGR1_CKOUTDIV_Pos);
529  }
530 
531  /* enable the DFSDM global interface */
532  DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
533  }
534 
535  /* Set channel input parameters */
536  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
537  DFSDM_CHCFGR1_CHINSEL);
538  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
539  hdfsdm_channel->Init.Input.DataPacking |
540  hdfsdm_channel->Init.Input.Pins);
541 
542  /* Set serial interface parameters */
543  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
544  hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
545  hdfsdm_channel->Init.SerialInterface.SpiClock);
546 
547  /* Set analog watchdog parameters */
548  hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
549  hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
550  ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
551 
552  /* Set channel offset and right bit shift */
553  hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
554  hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
555  (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
556 
557  /* Enable DFSDM channel */
558  hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
559 
560  /* Set DFSDM Channel to ready state */
561  hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
562 
563  /* Store channel handle in DFSDM channel handle table */
564  a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
565 #endif /* DFSDM2_Channel0 */
566 
567  return HAL_OK;
568 }
569 
575 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
576 {
577 #if defined(DFSDM2_Channel0)
578  __IO uint32_t* channelCounterPtr;
579  DFSDM_Channel_HandleTypeDef **channelHandleTable;
580  DFSDM_Channel_TypeDef* channel0Instance;
581 #endif /* defined(DFSDM2_Channel0) */
582 
583  /* Check DFSDM Channel handle */
584  if(hdfsdm_channel == NULL)
585  {
586  return HAL_ERROR;
587  }
588 
589  /* Check parameters */
590  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
591 
592 #if defined(DFSDM2_Channel0)
593  /* Get channel counter, channel handle table and channel 0 instance */
594  if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
595  {
596  channelCounterPtr = &v_dfsdm1ChannelCounter;
597  channelHandleTable = a_dfsdm1ChannelHandle;
598  channel0Instance = DFSDM1_Channel0;
599  }
600  else
601  {
602  channelCounterPtr = &v_dfsdm2ChannelCounter;
603  channelHandleTable = a_dfsdm2ChannelHandle;
604  channel0Instance = DFSDM2_Channel0;
605  }
606 
607  /* Check that channel has not been already deinitialized */
608  if(channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
609  {
610  return HAL_ERROR;
611  }
612 
613  /* Disable the DFSDM channel */
614  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
615 
616  /* Update the channel counter */
617  (*channelCounterPtr)--;
618 
619  /* Disable global DFSDM at deinit of last channel */
620  if(*channelCounterPtr == 0U)
621  {
622  channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
623  }
624 
625  /* Call MSP deinit function */
626 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
627  if(hdfsdm_channel->MspDeInitCallback == NULL)
628  {
629  hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
630  }
631  hdfsdm_channel->MspDeInitCallback(hdfsdm_channel);
632 #else
633  HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
634 #endif
635 
636  /* Set DFSDM Channel in reset state */
637  hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
638 
639  /* Reset channel handle in DFSDM channel handle table */
640  channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = NULL;
641 #else
642  /* Check that channel has not been already deinitialized */
643  if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
644  {
645  return HAL_ERROR;
646  }
647 
648  /* Disable the DFSDM channel */
649  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
650 
651  /* Update the channel counter */
652  v_dfsdm1ChannelCounter--;
653 
654  /* Disable global DFSDM at deinit of last channel */
655  if(v_dfsdm1ChannelCounter == 0U)
656  {
657  DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
658  }
659 
660  /* Call MSP deinit function */
661 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
662  if(hdfsdm_channel->MspDeInitCallback == NULL)
663  {
664  hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
665  }
666  hdfsdm_channel->MspDeInitCallback(hdfsdm_channel);
667 #else
668  HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
669 #endif
670 
671  /* Set DFSDM Channel in reset state */
672  hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
673 
674  /* Reset channel handle in DFSDM channel handle table */
675  a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;
676 #endif /* defined(DFSDM2_Channel0) */
677 
678  return HAL_OK;
679 }
680 
686 __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
687 {
688  /* Prevent unused argument(s) compilation warning */
689  UNUSED(hdfsdm_channel);
690  /* NOTE : This function should not be modified, when the function is needed,
691  the HAL_DFSDM_ChannelMspInit could be implemented in the user file.
692  */
693 }
694 
700 __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
701 {
702  /* Prevent unused argument(s) compilation warning */
703  UNUSED(hdfsdm_channel);
704  /* NOTE : This function should not be modified, when the function is needed,
705  the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.
706  */
707 }
708 
709 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
723 HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
724  HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,
725  pDFSDM_Channel_CallbackTypeDef pCallback)
726 {
727  HAL_StatusTypeDef status = HAL_OK;
728 
729  if(pCallback == NULL)
730  {
731  /* update return status */
732  status = HAL_ERROR;
733  }
734  else
735  {
736  if(HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State)
737  {
738  switch (CallbackID)
739  {
740  case HAL_DFSDM_CHANNEL_CKAB_CB_ID :
741  hdfsdm_channel->CkabCallback = pCallback;
742  break;
743  case HAL_DFSDM_CHANNEL_SCD_CB_ID :
744  hdfsdm_channel->ScdCallback = pCallback;
745  break;
746  case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
747  hdfsdm_channel->MspInitCallback = pCallback;
748  break;
749  case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
750  hdfsdm_channel->MspDeInitCallback = pCallback;
751  break;
752  default :
753  /* update return status */
754  status = HAL_ERROR;
755  break;
756  }
757  }
758  else if(HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)
759  {
760  switch (CallbackID)
761  {
762  case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
763  hdfsdm_channel->MspInitCallback = pCallback;
764  break;
765  case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
766  hdfsdm_channel->MspDeInitCallback = pCallback;
767  break;
768  default :
769  /* update return status */
770  status = HAL_ERROR;
771  break;
772  }
773  }
774  else
775  {
776  /* update return status */
777  status = HAL_ERROR;
778  }
779  }
780  return status;
781 }
782 
795 HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
796  HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID)
797 {
798  HAL_StatusTypeDef status = HAL_OK;
799 
800  if(HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State)
801  {
802  switch (CallbackID)
803  {
804  case HAL_DFSDM_CHANNEL_CKAB_CB_ID :
805  hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
806  break;
807  case HAL_DFSDM_CHANNEL_SCD_CB_ID :
808  hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback;
809  break;
810  case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
811  hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
812  break;
813  case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
814  hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
815  break;
816  default :
817  /* update return status */
818  status = HAL_ERROR;
819  break;
820  }
821  }
822  else if(HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State)
823  {
824  switch (CallbackID)
825  {
826  case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID :
827  hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit;
828  break;
829  case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID :
830  hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
831  break;
832  default :
833  /* update return status */
834  status = HAL_ERROR;
835  break;
836  }
837  }
838  else
839  {
840  /* update return status */
841  status = HAL_ERROR;
842  }
843  return status;
844 }
845 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
875 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
876 {
877  HAL_StatusTypeDef status = HAL_OK;
878  uint32_t tickstart;
879  uint32_t channel;
880 
881 #if defined(DFSDM2_Channel0)
882  DFSDM_Filter_TypeDef* filter0Instance;
883 #endif /* defined(DFSDM2_Channel0) */
884 
885  /* Check parameters */
886  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
887 
888  /* Check DFSDM channel state */
889  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
890  {
891  /* Return error status */
892  status = HAL_ERROR;
893  }
894  else
895  {
896 #if defined (DFSDM2_Channel0)
897  /* Get channel counter, channel handle table and channel 0 instance */
898  if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
899  {
900  filter0Instance = DFSDM1_Filter0;
901  }
902  else
903  {
904  filter0Instance = DFSDM2_Filter0;
905  }
906  /* Get channel number from channel instance */
907  channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
908 
909  /* Get timeout */
910  tickstart = HAL_GetTick();
911 
912  /* Clear clock absence flag */
913  while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
914  {
915  filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
916 
917  /* Check the Timeout */
918  if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
919  {
920  /* Set timeout status */
921  status = HAL_TIMEOUT;
922  break;
923  }
924  }
925 #else
926  /* Get channel number from channel instance */
927  channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
928 
929  /* Get timeout */
930  tickstart = HAL_GetTick();
931 
932  /* Clear clock absence flag */
933  while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
934  {
935  DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
936 
937  /* Check the Timeout */
938  if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
939  {
940  /* Set timeout status */
941  status = HAL_TIMEOUT;
942  break;
943  }
944  }
945 #endif /* DFSDM2_Channel0 */
946 
947  if(status == HAL_OK)
948  {
949  /* Start clock absence detection */
950  hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
951  }
952  }
953  /* Return function status */
954  return status;
955 }
956 
963 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
964  uint32_t Timeout)
965 {
966  uint32_t tickstart;
967  uint32_t channel;
968 #if defined(DFSDM2_Channel0)
969  DFSDM_Filter_TypeDef* filter0Instance;
970 #endif /* defined(DFSDM2_Channel0) */
971 
972  /* Check parameters */
973  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
974 
975  /* Check DFSDM channel state */
976  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
977  {
978  /* Return error status */
979  return HAL_ERROR;
980  }
981  else
982  {
983 #if defined(DFSDM2_Channel0)
984 
985  /* Get channel counter, channel handle table and channel 0 instance */
986  if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
987  {
988  filter0Instance = DFSDM1_Filter0;
989  }
990  else
991  {
992  filter0Instance = DFSDM2_Filter0;
993  }
994 
995  /* Get channel number from channel instance */
996  channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
997 
998  /* Get timeout */
999  tickstart = HAL_GetTick();
1000 
1001  /* Wait clock absence detection */
1002  while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U)
1003  {
1004  /* Check the Timeout */
1005  if(Timeout != HAL_MAX_DELAY)
1006  {
1007  if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
1008  {
1009  /* Return timeout status */
1010  return HAL_TIMEOUT;
1011  }
1012  }
1013  }
1014 
1015  /* Clear clock absence detection flag */
1016  filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
1017 #else
1018  /* Get channel number from channel instance */
1019  channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1020 
1021  /* Get timeout */
1022  tickstart = HAL_GetTick();
1023 
1024  /* Wait clock absence detection */
1025  while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U)
1026  {
1027  /* Check the Timeout */
1028  if(Timeout != HAL_MAX_DELAY)
1029  {
1030  if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
1031  {
1032  /* Return timeout status */
1033  return HAL_TIMEOUT;
1034  }
1035  }
1036  }
1037 
1038  /* Clear clock absence detection flag */
1039  DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
1040 #endif /* defined(DFSDM2_Channel0) */
1041  /* Return function status */
1042  return HAL_OK;
1043  }
1044 }
1045 
1051 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1052 {
1053  HAL_StatusTypeDef status = HAL_OK;
1054  uint32_t channel;
1055 #if defined(DFSDM2_Channel0)
1056  DFSDM_Filter_TypeDef* filter0Instance;
1057 #endif /* defined(DFSDM2_Channel0) */
1058 
1059  /* Check parameters */
1060  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1061 
1062  /* Check DFSDM channel state */
1063  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1064  {
1065  /* Return error status */
1066  status = HAL_ERROR;
1067  }
1068  else
1069  {
1070 #if defined(DFSDM2_Channel0)
1071 
1072  /* Get channel counter, channel handle table and channel 0 instance */
1073  if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
1074  {
1075  filter0Instance = DFSDM1_Filter0;
1076  }
1077  else
1078  {
1079  filter0Instance = DFSDM2_Filter0;
1080  }
1081 
1082  /* Stop clock absence detection */
1083  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
1084 
1085  /* Clear clock absence flag */
1086  channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1087  filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
1088 
1089 #else
1090  /* Stop clock absence detection */
1091  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
1092 
1093  /* Clear clock absence flag */
1094  channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1095  DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
1096 #endif /* DFSDM2_Channel0 */
1097  }
1098  /* Return function status */
1099  return status;
1100 }
1101 
1111 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1112 {
1113  HAL_StatusTypeDef status = HAL_OK;
1114  uint32_t channel;
1115  uint32_t tickstart;
1116 #if defined(DFSDM2_Channel0)
1117  DFSDM_Filter_TypeDef* filter0Instance;
1118 #endif /* defined(DFSDM2_Channel0) */
1119 
1120  /* Check parameters */
1121  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1122 
1123  /* Check DFSDM channel state */
1124  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1125  {
1126  /* Return error status */
1127  status = HAL_ERROR;
1128  }
1129  else
1130  {
1131 #if defined(DFSDM2_Channel0)
1132 
1133  /* Get channel counter, channel handle table and channel 0 instance */
1134  if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
1135  {
1136  filter0Instance = DFSDM1_Filter0;
1137  }
1138  else
1139  {
1140  filter0Instance = DFSDM2_Filter0;
1141  }
1142 
1143  /* Get channel number from channel instance */
1144  channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1145 
1146  /* Get timeout */
1147  tickstart = HAL_GetTick();
1148 
1149  /* Clear clock absence flag */
1150  while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
1151  {
1152  filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
1153 
1154  /* Check the Timeout */
1155  if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
1156  {
1157  /* Set timeout status */
1158  status = HAL_TIMEOUT;
1159  break;
1160  }
1161  }
1162 
1163  if(status == HAL_OK)
1164  {
1165  /* Activate clock absence detection interrupt */
1166  filter0Instance->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
1167 
1168  /* Start clock absence detection */
1169  hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
1170  }
1171 #else
1172  /* Get channel number from channel instance */
1173  channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1174 
1175  /* Get timeout */
1176  tickstart = HAL_GetTick();
1177 
1178  /* Clear clock absence flag */
1179  while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
1180  {
1181  DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
1182 
1183  /* Check the Timeout */
1184  if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
1185  {
1186  /* Set timeout status */
1187  status = HAL_TIMEOUT;
1188  break;
1189  }
1190  }
1191 
1192  if(status == HAL_OK)
1193  {
1194  /* Activate clock absence detection interrupt */
1195  DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
1196 
1197  /* Start clock absence detection */
1198  hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
1199  }
1200 
1201 #endif /* defined(DFSDM2_Channel0) */
1202  }
1203  /* Return function status */
1204  return status;
1205 }
1206 
1212 __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1213 {
1214  /* Prevent unused argument(s) compilation warning */
1215  UNUSED(hdfsdm_channel);
1216  /* NOTE : This function should not be modified, when the callback is needed,
1217  the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file
1218  */
1219 }
1220 
1227 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1228 {
1229  HAL_StatusTypeDef status = HAL_OK;
1230  uint32_t channel;
1231 #if defined(DFSDM2_Channel0)
1232  DFSDM_Filter_TypeDef* filter0Instance;
1233 #endif /* defined(DFSDM2_Channel0) */
1234 
1235  /* Check parameters */
1236  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1237 
1238  /* Check DFSDM channel state */
1239  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1240  {
1241  /* Return error status */
1242  status = HAL_ERROR;
1243  }
1244  else
1245  {
1246 #if defined(DFSDM2_Channel0)
1247 
1248  /* Get channel counter, channel handle table and channel 0 instance */
1249  if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
1250  {
1251  filter0Instance = DFSDM1_Filter0;
1252  }
1253  else
1254  {
1255  filter0Instance = DFSDM2_Filter0;
1256  }
1257 
1258  /* Stop clock absence detection */
1259  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
1260 
1261  /* Clear clock absence flag */
1262  channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1263  filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
1264 
1265  /* Disable clock absence detection interrupt */
1266  filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
1267 #else
1268 
1269  /* Stop clock absence detection */
1270  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
1271 
1272  /* Clear clock absence flag */
1273  channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1274  DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
1275 
1276  /* Disable clock absence detection interrupt */
1277  DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
1278 #endif /* DFSDM2_Channel0 */
1279  }
1280 
1281  /* Return function status */
1282  return status;
1283 }
1284 
1295 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
1296  uint32_t Threshold,
1297  uint32_t BreakSignal)
1298 {
1299  HAL_StatusTypeDef status = HAL_OK;
1300 
1301  /* Check parameters */
1302  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1303  assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
1304  assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
1305 
1306  /* Check DFSDM channel state */
1307  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1308  {
1309  /* Return error status */
1310  status = HAL_ERROR;
1311  }
1312  else
1313  {
1314  /* Configure threshold and break signals */
1315  hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
1316  hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
1317  Threshold);
1318 
1319  /* Start short circuit detection */
1320  hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
1321  }
1322  /* Return function status */
1323  return status;
1324 }
1325 
1332 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
1333  uint32_t Timeout)
1334 {
1335  uint32_t tickstart;
1336  uint32_t channel;
1337 #if defined(DFSDM2_Channel0)
1338  DFSDM_Filter_TypeDef* filter0Instance;
1339 #endif /* defined(DFSDM2_Channel0) */
1340 
1341  /* Check parameters */
1342  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1343 
1344  /* Check DFSDM channel state */
1345  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1346  {
1347  /* Return error status */
1348  return HAL_ERROR;
1349  }
1350  else
1351  {
1352  /* Get channel number from channel instance */
1353  channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1354 
1355 #if defined(DFSDM2_Channel0)
1356  /* Get channel counter, channel handle table and channel 0 instance */
1357  if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
1358  {
1359  filter0Instance = DFSDM1_Filter0;
1360  }
1361  else
1362  {
1363  filter0Instance = DFSDM2_Filter0;
1364  }
1365 
1366  /* Get timeout */
1367  tickstart = HAL_GetTick();
1368 
1369  /* Wait short circuit detection */
1370  while(((filter0Instance->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U)
1371  {
1372  /* Check the Timeout */
1373  if(Timeout != HAL_MAX_DELAY)
1374  {
1375  if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
1376  {
1377  /* Return timeout status */
1378  return HAL_TIMEOUT;
1379  }
1380  }
1381  }
1382 
1383  /* Clear short circuit detection flag */
1384  filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
1385 
1386 #else
1387  /* Get timeout */
1388  tickstart = HAL_GetTick();
1389 
1390  /* Wait short circuit detection */
1391  while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U)
1392  {
1393  /* Check the Timeout */
1394  if(Timeout != HAL_MAX_DELAY)
1395  {
1396  if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
1397  {
1398  /* Return timeout status */
1399  return HAL_TIMEOUT;
1400  }
1401  }
1402  }
1403 
1404  /* Clear short circuit detection flag */
1405  DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
1406 #endif /* DFSDM2_Channel0 */
1407 
1408  /* Return function status */
1409  return HAL_OK;
1410  }
1411 }
1412 
1418 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1419 {
1420  HAL_StatusTypeDef status = HAL_OK;
1421  uint32_t channel;
1422 #if defined(DFSDM2_Channel0)
1423  DFSDM_Filter_TypeDef* filter0Instance;
1424 #endif /* defined(DFSDM2_Channel0) */
1425 
1426  /* Check parameters */
1427  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1428 
1429  /* Check DFSDM channel state */
1430  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1431  {
1432  /* Return error status */
1433  status = HAL_ERROR;
1434  }
1435  else
1436  {
1437  /* Stop short circuit detection */
1438  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
1439 
1440  /* Clear short circuit detection flag */
1441  channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1442 
1443 #if defined(DFSDM2_Channel0)
1444  /* Get channel counter, channel handle table and channel 0 instance */
1445  if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
1446  {
1447  filter0Instance = DFSDM1_Filter0;
1448  }
1449  else
1450  {
1451  filter0Instance = DFSDM2_Filter0;
1452  }
1453 
1454  filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
1455 #else
1456  DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
1457 #endif /* DFSDM2_Channel0*/
1458  }
1459  /* Return function status */
1460  return status;
1461 }
1462 
1473 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
1474  uint32_t Threshold,
1475  uint32_t BreakSignal)
1476 {
1477  HAL_StatusTypeDef status = HAL_OK;
1478 #if defined(DFSDM2_Channel0)
1479  DFSDM_Filter_TypeDef* filter0Instance;
1480 #endif /* defined(DFSDM2_Channel0) */
1481 
1482  /* Check parameters */
1483  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1484  assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
1485  assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
1486 
1487  /* Check DFSDM channel state */
1488  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1489  {
1490  /* Return error status */
1491  status = HAL_ERROR;
1492  }
1493  else
1494  {
1495 #if defined(DFSDM2_Channel0)
1496  /* Get channel counter, channel handle table and channel 0 instance */
1497  if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
1498  {
1499  filter0Instance = DFSDM1_Filter0;
1500  }
1501  else
1502  {
1503  filter0Instance = DFSDM2_Filter0;
1504  }
1505  /* Activate short circuit detection interrupt */
1506  filter0Instance->FLTCR2 |= DFSDM_FLTCR2_SCDIE;
1507 #else
1508  /* Activate short circuit detection interrupt */
1509  DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE;
1510 #endif /* DFSDM2_Channel0 */
1511 
1512  /* Configure threshold and break signals */
1513  hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
1514  hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
1515  Threshold);
1516 
1517  /* Start short circuit detection */
1518  hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
1519  }
1520  /* Return function status */
1521  return status;
1522 }
1523 
1529 __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1530 {
1531  /* Prevent unused argument(s) compilation warning */
1532  UNUSED(hdfsdm_channel);
1533  /* NOTE : This function should not be modified, when the callback is needed,
1534  the HAL_DFSDM_ChannelScdCallback could be implemented in the user file
1535  */
1536 }
1537 
1544 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1545 {
1546  HAL_StatusTypeDef status = HAL_OK;
1547  uint32_t channel;
1548 #if defined(DFSDM2_Channel0)
1549  DFSDM_Filter_TypeDef* filter0Instance;
1550 #endif /* defined(DFSDM2_Channel0) */
1551 
1552  /* Check parameters */
1553  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1554 
1555  /* Check DFSDM channel state */
1556  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1557  {
1558  /* Return error status */
1559  status = HAL_ERROR;
1560  }
1561  else
1562  {
1563  /* Stop short circuit detection */
1564  hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
1565 
1566  /* Clear short circuit detection flag */
1567  channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1568 #if defined(DFSDM2_Channel0)
1569  /* Get channel counter, channel handle table and channel 0 instance */
1570  if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
1571  {
1572  filter0Instance = DFSDM1_Filter0;
1573  }
1574  else
1575  {
1576  filter0Instance = DFSDM2_Filter0;
1577  }
1578 
1579  filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
1580 
1581  /* Disable short circuit detection interrupt */
1582  filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
1583 #else
1584  DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
1585 
1586  /* Disable short circuit detection interrupt */
1587  DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
1588 #endif /* DFSDM2_Channel0 */
1589  }
1590  /* Return function status */
1591  return status;
1592 }
1593 
1599 int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1600 {
1601  return (int16_t) hdfsdm_channel->Instance->CHWDATAR;
1602 }
1603 
1611 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
1612  int32_t Offset)
1613 {
1614  HAL_StatusTypeDef status = HAL_OK;
1615 
1616  /* Check parameters */
1617  assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1618  assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));
1619 
1620  /* Check DFSDM channel state */
1621  if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1622  {
1623  /* Return error status */
1624  status = HAL_ERROR;
1625  }
1626  else
1627  {
1628  /* Modify channel offset */
1629  hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);
1630  hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_Pos);
1631  }
1632  /* Return function status */
1633  return status;
1634 }
1635 
1658 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1659 {
1660  /* Return DFSDM channel handle state */
1661  return hdfsdm_channel->State;
1662 }
1663 
1688 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1689 {
1690  /* Check DFSDM Channel handle */
1691  if(hdfsdm_filter == NULL)
1692  {
1693  return HAL_ERROR;
1694  }
1695 
1696  /* Check parameters */
1697  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
1698  assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));
1699  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));
1700  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));
1701  assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));
1702  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));
1703  assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));
1704  assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));
1705  assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));
1706  assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));
1707 
1708  /* Check parameters compatibility */
1709  if((hdfsdm_filter->Instance == DFSDM1_Filter0) &&
1710  ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
1711  (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
1712  {
1713  return HAL_ERROR;
1714  }
1715 #if defined (DFSDM2_Channel0)
1716  if((hdfsdm_filter->Instance == DFSDM2_Filter0) &&
1717  ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
1718  (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
1719  {
1720  return HAL_ERROR;
1721  }
1722 #endif /* DFSDM2_Channel0 */
1723 
1724  /* Initialize DFSDM filter variables with default values */
1725  hdfsdm_filter->RegularContMode = DFSDM_CONTINUOUS_CONV_OFF;
1726  hdfsdm_filter->InjectedChannelsNbr = 1U;
1727  hdfsdm_filter->InjConvRemaining = 1U;
1728  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE;
1729 
1730 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
1731  /* Reset callback pointers to the weak predefined callbacks */
1732  hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback;
1733  hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback;
1734  hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback;
1735  hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback;
1736  hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback;
1737  hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback;
1738 
1739  /* Call MSP init function */
1740  if(hdfsdm_filter->MspInitCallback == NULL)
1741  {
1742  hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
1743  }
1744  hdfsdm_filter->MspInitCallback(hdfsdm_filter);
1745 #else
1746  /* Call MSP init function */
1747  HAL_DFSDM_FilterMspInit(hdfsdm_filter);
1748 #endif
1749 
1750  /* Set regular parameters */
1751  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
1752  if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)
1753  {
1754  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;
1755  }
1756  else
1757  {
1758  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);
1759  }
1760 
1761  if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)
1762  {
1763  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;
1764  }
1765  else
1766  {
1767  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);
1768  }
1769 
1770  /* Set injected parameters */
1771  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);
1772  if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)
1773  {
1774  assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));
1775  assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));
1776  hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);
1777  }
1778 
1779  if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)
1780  {
1781  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;
1782  }
1783  else
1784  {
1785  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);
1786  }
1787 
1788  if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)
1789  {
1790  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;
1791  }
1792  else
1793  {
1794  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);
1795  }
1796 
1797  /* Set filter parameters */
1798  hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
1799  hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
1800  ((hdfsdm_filter->Init.FilterParam.Oversampling - 1U) << DFSDM_FLTFCR_FOSR_Pos) |
1801  (hdfsdm_filter->Init.FilterParam.IntOversampling - 1U));
1802 
1803  /* Store regular and injected triggers and injected scan mode*/
1804  hdfsdm_filter->RegularTrigger = hdfsdm_filter->Init.RegularParam.Trigger;
1805  hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger;
1806  hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;
1807  hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;
1808 
1809  /* Enable DFSDM filter */
1810  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
1811 
1812  /* Set DFSDM filter to ready state */
1813  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;
1814 
1815  return HAL_OK;
1816 }
1817 
1823 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1824 {
1825  /* Check DFSDM filter handle */
1826  if(hdfsdm_filter == NULL)
1827  {
1828  return HAL_ERROR;
1829  }
1830 
1831  /* Check parameters */
1832  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
1833 
1834  /* Disable the DFSDM filter */
1835  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
1836 
1837  /* Call MSP deinit function */
1838 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
1839  if(hdfsdm_filter->MspDeInitCallback == NULL)
1840  {
1841  hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
1842  }
1843  hdfsdm_filter->MspDeInitCallback(hdfsdm_filter);
1844 #else
1845  HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);
1846 #endif
1847 
1848  /* Set DFSDM filter in reset state */
1849  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;
1850 
1851  return HAL_OK;
1852 }
1853 
1859 __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1860 {
1861  /* Prevent unused argument(s) compilation warning */
1862  UNUSED(hdfsdm_filter);
1863  /* NOTE : This function should not be modified, when the function is needed,
1864  the HAL_DFSDM_FilterMspInit could be implemented in the user file.
1865  */
1866 }
1867 
1873 __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1874 {
1875  /* Prevent unused argument(s) compilation warning */
1876  UNUSED(hdfsdm_filter);
1877  /* NOTE : This function should not be modified, when the function is needed,
1878  the HAL_DFSDM_FilterMspDeInit could be implemented in the user file.
1879  */
1880 }
1881 
1882 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
1899 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
1900  HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,
1901  pDFSDM_Filter_CallbackTypeDef pCallback)
1902 {
1903  HAL_StatusTypeDef status = HAL_OK;
1904 
1905  if(pCallback == NULL)
1906  {
1907  /* update the error code */
1908  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
1909  /* update return status */
1910  status = HAL_ERROR;
1911  }
1912  else
1913  {
1914  if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
1915  {
1916  switch (CallbackID)
1917  {
1918  case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :
1919  hdfsdm_filter->RegConvCpltCallback = pCallback;
1920  break;
1921  case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :
1922  hdfsdm_filter->RegConvHalfCpltCallback = pCallback;
1923  break;
1924  case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :
1925  hdfsdm_filter->InjConvCpltCallback = pCallback;
1926  break;
1927  case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :
1928  hdfsdm_filter->InjConvHalfCpltCallback = pCallback;
1929  break;
1930  case HAL_DFSDM_FILTER_ERROR_CB_ID :
1931  hdfsdm_filter->ErrorCallback = pCallback;
1932  break;
1933  case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
1934  hdfsdm_filter->MspInitCallback = pCallback;
1935  break;
1936  case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
1937  hdfsdm_filter->MspDeInitCallback = pCallback;
1938  break;
1939  default :
1940  /* update the error code */
1941  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
1942  /* update return status */
1943  status = HAL_ERROR;
1944  break;
1945  }
1946  }
1947  else if(HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State)
1948  {
1949  switch (CallbackID)
1950  {
1951  case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
1952  hdfsdm_filter->MspInitCallback = pCallback;
1953  break;
1954  case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
1955  hdfsdm_filter->MspDeInitCallback = pCallback;
1956  break;
1957  default :
1958  /* update the error code */
1959  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
1960  /* update return status */
1961  status = HAL_ERROR;
1962  break;
1963  }
1964  }
1965  else
1966  {
1967  /* update the error code */
1968  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
1969  /* update return status */
1970  status = HAL_ERROR;
1971  }
1972  }
1973  return status;
1974 }
1975 
1991 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
1992  HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID)
1993 {
1994  HAL_StatusTypeDef status = HAL_OK;
1995 
1996  if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
1997  {
1998  switch (CallbackID)
1999  {
2000  case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID :
2001  hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback;
2002  break;
2003  case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID :
2004  hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback;
2005  break;
2006  case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID :
2007  hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback;
2008  break;
2009  case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID :
2010  hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback;
2011  break;
2012  case HAL_DFSDM_FILTER_ERROR_CB_ID :
2013  hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback;
2014  break;
2015  case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
2016  hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
2017  break;
2018  case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
2019  hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
2020  break;
2021  default :
2022  /* update the error code */
2023  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
2024  /* update return status */
2025  status = HAL_ERROR;
2026  break;
2027  }
2028  }
2029  else if(HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State)
2030  {
2031  switch (CallbackID)
2032  {
2033  case HAL_DFSDM_FILTER_MSPINIT_CB_ID :
2034  hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit;
2035  break;
2036  case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID :
2037  hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
2038  break;
2039  default :
2040  /* update the error code */
2041  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
2042  /* update return status */
2043  status = HAL_ERROR;
2044  break;
2045  }
2046  }
2047  else
2048  {
2049  /* update the error code */
2050  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
2051  /* update return status */
2052  status = HAL_ERROR;
2053  }
2054  return status;
2055 }
2056 
2064 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2065  pDFSDM_Filter_AwdCallbackTypeDef pCallback)
2066 {
2067  HAL_StatusTypeDef status = HAL_OK;
2068 
2069  if(pCallback == NULL)
2070  {
2071  /* update the error code */
2072  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
2073  /* update return status */
2074  status = HAL_ERROR;
2075  }
2076  else
2077  {
2078  if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
2079  {
2080  hdfsdm_filter->AwdCallback = pCallback;
2081  }
2082  else
2083  {
2084  /* update the error code */
2085  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
2086  /* update return status */
2087  status = HAL_ERROR;
2088  }
2089  }
2090  return status;
2091 }
2092 
2099 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2100 {
2101  HAL_StatusTypeDef status = HAL_OK;
2102 
2103  if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State)
2104  {
2105  hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback;
2106  }
2107  else
2108  {
2109  /* update the error code */
2110  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK;
2111  /* update return status */
2112  status = HAL_ERROR;
2113  }
2114  return status;
2115 }
2116 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
2145 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2146  uint32_t Channel,
2147  uint32_t ContinuousMode)
2148 {
2149  HAL_StatusTypeDef status = HAL_OK;
2150 
2151  /* Check parameters */
2152  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2153  assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));
2154  assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));
2155 
2156  /* Check DFSDM filter state */
2157  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
2158  (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
2159  {
2160  /* Configure channel and continuous mode for regular conversion */
2161  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);
2162  if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)
2163  {
2164  hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |
2165  DFSDM_FLTCR1_RCONT);
2166  }
2167  else
2168  {
2169  hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);
2170  }
2171  /* Store continuous mode information */
2172  hdfsdm_filter->RegularContMode = ContinuousMode;
2173  }
2174  else
2175  {
2176  status = HAL_ERROR;
2177  }
2178 
2179  /* Return function status */
2180  return status;
2181 }
2182 
2190 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2191  uint32_t Channel)
2192 {
2193  HAL_StatusTypeDef status = HAL_OK;
2194 
2195  /* Check parameters */
2196  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2197  assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
2198 
2199  /* Check DFSDM filter state */
2200  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
2201  (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
2202  {
2203  /* Configure channel for injected conversion */
2204  hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK);
2205  /* Store number of injected channels */
2206  hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);
2207  /* Update number of injected channels remaining */
2208  hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
2209  hdfsdm_filter->InjectedChannelsNbr : 1U;
2210  }
2211  else
2212  {
2213  status = HAL_ERROR;
2214  }
2215  /* Return function status */
2216  return status;
2217 }
2218 
2260 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2261 {
2262  HAL_StatusTypeDef status = HAL_OK;
2263 
2264  /* Check parameters */
2265  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2266 
2267  /* Check DFSDM filter state */
2268  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2269  (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
2270  {
2271  /* Start regular conversion */
2272  DFSDM_RegConvStart(hdfsdm_filter);
2273  }
2274  else
2275  {
2276  status = HAL_ERROR;
2277  }
2278  /* Return function status */
2279  return status;
2280 }
2281 
2289 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2290  uint32_t Timeout)
2291 {
2292  uint32_t tickstart;
2293 
2294  /* Check parameters */
2295  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2296 
2297  /* Check DFSDM filter state */
2298  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
2299  (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2300  {
2301  /* Return error status */
2302  return HAL_ERROR;
2303  }
2304  else
2305  {
2306  /* Get timeout */
2307  tickstart = HAL_GetTick();
2308 
2309  /* Wait end of regular conversion */
2310  while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)
2311  {
2312  /* Check the Timeout */
2313  if(Timeout != HAL_MAX_DELAY)
2314  {
2315  if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
2316  {
2317  /* Return timeout status */
2318  return HAL_TIMEOUT;
2319  }
2320  }
2321  }
2322  /* Check if overrun occurs */
2323  if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)
2324  {
2325  /* Update error code and call error callback */
2326  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
2327 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
2328  hdfsdm_filter->ErrorCallback(hdfsdm_filter);
2329 #else
2330  HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
2331 #endif
2332 
2333  /* Clear regular overrun flag */
2334  hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
2335  }
2336  /* Update DFSDM filter state only if not continuous conversion and SW trigger */
2337  if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
2338  (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
2339  {
2340  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
2341  HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
2342  }
2343  /* Return function status */
2344  return HAL_OK;
2345  }
2346 }
2347 
2354 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2355 {
2356  HAL_StatusTypeDef status = HAL_OK;
2357 
2358  /* Check parameters */
2359  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2360 
2361  /* Check DFSDM filter state */
2362  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
2363  (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2364  {
2365  /* Return error status */
2366  status = HAL_ERROR;
2367  }
2368  else
2369  {
2370  /* Stop regular conversion */
2371  DFSDM_RegConvStop(hdfsdm_filter);
2372  }
2373  /* Return function status */
2374  return status;
2375 }
2376 
2384 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2385 {
2386  HAL_StatusTypeDef status = HAL_OK;
2387 
2388  /* Check parameters */
2389  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2390 
2391  /* Check DFSDM filter state */
2392  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2393  (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
2394  {
2395  /* Enable interrupts for regular conversions */
2396  hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
2397 
2398  /* Start regular conversion */
2399  DFSDM_RegConvStart(hdfsdm_filter);
2400  }
2401  else
2402  {
2403  status = HAL_ERROR;
2404  }
2405  /* Return function status */
2406  return status;
2407 }
2408 
2415 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2416 {
2417  HAL_StatusTypeDef status = HAL_OK;
2418 
2419  /* Check parameters */
2420  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2421 
2422  /* Check DFSDM filter state */
2423  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
2424  (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2425  {
2426  /* Return error status */
2427  status = HAL_ERROR;
2428  }
2429  else
2430  {
2431  /* Disable interrupts for regular conversions */
2432  hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
2433 
2434  /* Stop regular conversion */
2435  DFSDM_RegConvStop(hdfsdm_filter);
2436  }
2437  /* Return function status */
2438  return status;
2439 }
2440 
2453 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2454  int32_t *pData,
2455  uint32_t Length)
2456 {
2457  HAL_StatusTypeDef status = HAL_OK;
2458 
2459  /* Check parameters */
2460  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2461 
2462  /* Check destination address and length */
2463  if((pData == NULL) || (Length == 0U))
2464  {
2465  status = HAL_ERROR;
2466  }
2467  /* Check that DMA is enabled for regular conversion */
2468  else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
2469  {
2470  status = HAL_ERROR;
2471  }
2472  /* Check parameters compatibility */
2473  else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2474  (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
2475  (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
2476  (Length != 1U))
2477  {
2478  status = HAL_ERROR;
2479  }
2480  else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2481  (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
2482  (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
2483  {
2484  status = HAL_ERROR;
2485  }
2486  /* Check DFSDM filter state */
2487  else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2488  (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
2489  {
2490  /* Set callbacks on DMA handler */
2491  hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
2492  hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
2493  hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
2494  DFSDM_DMARegularHalfConvCplt : NULL;
2495 
2496  /* Start DMA in interrupt mode */
2497  if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \
2498  (uint32_t) pData, Length) != HAL_OK)
2499  {
2500  /* Set DFSDM filter in error state */
2501  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
2502  status = HAL_ERROR;
2503  }
2504  else
2505  {
2506  /* Start regular conversion */
2507  DFSDM_RegConvStart(hdfsdm_filter);
2508  }
2509  }
2510  else
2511  {
2512  status = HAL_ERROR;
2513  }
2514  /* Return function status */
2515  return status;
2516 }
2517 
2530 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2531  int16_t *pData,
2532  uint32_t Length)
2533 {
2534  HAL_StatusTypeDef status = HAL_OK;
2535 
2536  /* Check parameters */
2537  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2538 
2539  /* Check destination address and length */
2540  if((pData == NULL) || (Length == 0U))
2541  {
2542  status = HAL_ERROR;
2543  }
2544  /* Check that DMA is enabled for regular conversion */
2545  else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
2546  {
2547  status = HAL_ERROR;
2548  }
2549  /* Check parameters compatibility */
2550  else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2551  (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
2552  (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
2553  (Length != 1U))
2554  {
2555  status = HAL_ERROR;
2556  }
2557  else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2558  (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
2559  (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
2560  {
2561  status = HAL_ERROR;
2562  }
2563  /* Check DFSDM filter state */
2564  else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2565  (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
2566  {
2567  /* Set callbacks on DMA handler */
2568  hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
2569  hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
2570  hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
2571  DFSDM_DMARegularHalfConvCplt : NULL;
2572 
2573  /* Start DMA in interrupt mode */
2574  if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \
2575  (uint32_t) pData, Length) != HAL_OK)
2576  {
2577  /* Set DFSDM filter in error state */
2578  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
2579  status = HAL_ERROR;
2580  }
2581  else
2582  {
2583  /* Start regular conversion */
2584  DFSDM_RegConvStart(hdfsdm_filter);
2585  }
2586  }
2587  else
2588  {
2589  status = HAL_ERROR;
2590  }
2591  /* Return function status */
2592  return status;
2593 }
2594 
2601 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2602 {
2603  HAL_StatusTypeDef status = HAL_OK;
2604 
2605  /* Check parameters */
2606  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2607 
2608  /* Check DFSDM filter state */
2609  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
2610  (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2611  {
2612  /* Return error status */
2613  status = HAL_ERROR;
2614  }
2615  else
2616  {
2617  /* Stop current DMA transfer */
2618  if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)
2619  {
2620  /* Set DFSDM filter in error state */
2621  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
2622  status = HAL_ERROR;
2623  }
2624  else
2625  {
2626  /* Stop regular conversion */
2627  DFSDM_RegConvStop(hdfsdm_filter);
2628  }
2629  }
2630  /* Return function status */
2631  return status;
2632 }
2633 
2640 int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2641  uint32_t *Channel)
2642 {
2643  uint32_t reg = 0U;
2644  int32_t value = 0;
2645 
2646  /* Check parameters */
2647  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2648  assert_param(Channel != NULL);
2649 
2650  /* Get value of data register for regular channel */
2651  reg = hdfsdm_filter->Instance->FLTRDATAR;
2652 
2653  /* Extract channel and regular conversion value */
2654  *Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
2655  value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_RDATA_Pos);
2656 
2657  /* return regular conversion value */
2658  return value;
2659 }
2660 
2668 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2669 {
2670  HAL_StatusTypeDef status = HAL_OK;
2671 
2672  /* Check parameters */
2673  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2674 
2675  /* Check DFSDM filter state */
2676  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2677  (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
2678  {
2679  /* Start injected conversion */
2680  DFSDM_InjConvStart(hdfsdm_filter);
2681  }
2682  else
2683  {
2684  status = HAL_ERROR;
2685  }
2686  /* Return function status */
2687  return status;
2688 }
2689 
2697 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2698  uint32_t Timeout)
2699 {
2700  uint32_t tickstart;
2701 
2702  /* Check parameters */
2703  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2704 
2705  /* Check DFSDM filter state */
2706  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
2707  (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2708  {
2709  /* Return error status */
2710  return HAL_ERROR;
2711  }
2712  else
2713  {
2714  /* Get timeout */
2715  tickstart = HAL_GetTick();
2716 
2717  /* Wait end of injected conversions */
2718  while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)
2719  {
2720  /* Check the Timeout */
2721  if(Timeout != HAL_MAX_DELAY)
2722  {
2723  if( ((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
2724  {
2725  /* Return timeout status */
2726  return HAL_TIMEOUT;
2727  }
2728  }
2729  }
2730  /* Check if overrun occurs */
2731  if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)
2732  {
2733  /* Update error code and call error callback */
2734  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
2735 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
2736  hdfsdm_filter->ErrorCallback(hdfsdm_filter);
2737 #else
2738  HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
2739 #endif
2740 
2741  /* Clear injected overrun flag */
2742  hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
2743  }
2744 
2745  /* Update remaining injected conversions */
2746  hdfsdm_filter->InjConvRemaining--;
2747  if(hdfsdm_filter->InjConvRemaining == 0U)
2748  {
2749  /* Update DFSDM filter state only if trigger is software */
2750  if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
2751  {
2752  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
2753  HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
2754  }
2755 
2756  /* end of injected sequence, reset the value */
2757  hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
2758  hdfsdm_filter->InjectedChannelsNbr : 1U;
2759  }
2760 
2761  /* Return function status */
2762  return HAL_OK;
2763  }
2764 }
2765 
2772 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2773 {
2774  HAL_StatusTypeDef status = HAL_OK;
2775 
2776  /* Check parameters */
2777  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2778 
2779  /* Check DFSDM filter state */
2780  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
2781  (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2782  {
2783  /* Return error status */
2784  status = HAL_ERROR;
2785  }
2786  else
2787  {
2788  /* Stop injected conversion */
2789  DFSDM_InjConvStop(hdfsdm_filter);
2790  }
2791  /* Return function status */
2792  return status;
2793 }
2794 
2802 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2803 {
2804  HAL_StatusTypeDef status = HAL_OK;
2805 
2806  /* Check parameters */
2807  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2808 
2809  /* Check DFSDM filter state */
2810  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2811  (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
2812  {
2813  /* Enable interrupts for injected conversions */
2814  hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
2815 
2816  /* Start injected conversion */
2817  DFSDM_InjConvStart(hdfsdm_filter);
2818  }
2819  else
2820  {
2821  status = HAL_ERROR;
2822  }
2823  /* Return function status */
2824  return status;
2825 }
2826 
2833 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2834 {
2835  HAL_StatusTypeDef status = HAL_OK;
2836 
2837  /* Check parameters */
2838  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2839 
2840  /* Check DFSDM filter state */
2841  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
2842  (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2843  {
2844  /* Return error status */
2845  status = HAL_ERROR;
2846  }
2847  else
2848  {
2849  /* Disable interrupts for injected conversions */
2850  hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
2851 
2852  /* Stop injected conversion */
2853  DFSDM_InjConvStop(hdfsdm_filter);
2854  }
2855  /* Return function status */
2856  return status;
2857 }
2858 
2871 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2872  int32_t *pData,
2873  uint32_t Length)
2874 {
2875  HAL_StatusTypeDef status = HAL_OK;
2876 
2877  /* Check parameters */
2878  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2879 
2880  /* Check destination address and length */
2881  if((pData == NULL) || (Length == 0U))
2882  {
2883  status = HAL_ERROR;
2884  }
2885  /* Check that DMA is enabled for injected conversion */
2886  else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
2887  {
2888  status = HAL_ERROR;
2889  }
2890  /* Check parameters compatibility */
2891  else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2892  (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
2893  (Length > hdfsdm_filter->InjConvRemaining))
2894  {
2895  status = HAL_ERROR;
2896  }
2897  else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2898  (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
2899  {
2900  status = HAL_ERROR;
2901  }
2902  /* Check DFSDM filter state */
2903  else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2904  (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
2905  {
2906  /* Set callbacks on DMA handler */
2907  hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
2908  hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
2909  hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
2910  DFSDM_DMAInjectedHalfConvCplt : NULL;
2911 
2912  /* Start DMA in interrupt mode */
2913  if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \
2914  (uint32_t) pData, Length) != HAL_OK)
2915  {
2916  /* Set DFSDM filter in error state */
2917  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
2918  status = HAL_ERROR;
2919  }
2920  else
2921  {
2922  /* Start injected conversion */
2923  DFSDM_InjConvStart(hdfsdm_filter);
2924  }
2925  }
2926  else
2927  {
2928  status = HAL_ERROR;
2929  }
2930  /* Return function status */
2931  return status;
2932 }
2933 
2946 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2947  int16_t *pData,
2948  uint32_t Length)
2949 {
2950  HAL_StatusTypeDef status = HAL_OK;
2951 
2952  /* Check parameters */
2953  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2954 
2955  /* Check destination address and length */
2956  if((pData == NULL) || (Length == 0U))
2957  {
2958  status = HAL_ERROR;
2959  }
2960  /* Check that DMA is enabled for injected conversion */
2961  else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
2962  {
2963  status = HAL_ERROR;
2964  }
2965  /* Check parameters compatibility */
2966  else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2967  (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
2968  (Length > hdfsdm_filter->InjConvRemaining))
2969  {
2970  status = HAL_ERROR;
2971  }
2972  else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2973  (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
2974  {
2975  status = HAL_ERROR;
2976  }
2977  /* Check DFSDM filter state */
2978  else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2979  (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
2980  {
2981  /* Set callbacks on DMA handler */
2982  hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
2983  hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
2984  hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
2985  DFSDM_DMAInjectedHalfConvCplt : NULL;
2986 
2987  /* Start DMA in interrupt mode */
2988  if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \
2989  (uint32_t) pData, Length) != HAL_OK)
2990  {
2991  /* Set DFSDM filter in error state */
2992  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
2993  status = HAL_ERROR;
2994  }
2995  else
2996  {
2997  /* Start injected conversion */
2998  DFSDM_InjConvStart(hdfsdm_filter);
2999  }
3000  }
3001  else
3002  {
3003  status = HAL_ERROR;
3004  }
3005  /* Return function status */
3006  return status;
3007 }
3008 
3015 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3016 {
3017  HAL_StatusTypeDef status = HAL_OK;
3018 
3019  /* Check parameters */
3020  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
3021 
3022  /* Check DFSDM filter state */
3023  if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
3024  (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
3025  {
3026  /* Return error status */
3027  status = HAL_ERROR;
3028  }
3029  else
3030  {
3031  /* Stop current DMA transfer */
3032  if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)
3033  {
3034  /* Set DFSDM filter in error state */
3035  hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
3036  status = HAL_ERROR;
3037  }
3038  else
3039  {
3040  /* Stop regular conversion */
3041  DFSDM_InjConvStop(hdfsdm_filter);
3042  }
3043  }
3044  /* Return function status */
3045  return status;
3046 }
3047 
3054 int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
3055  uint32_t *Channel)
3056 {
3057  uint32_t reg = 0U;
3058  int32_t value = 0;
3059 
3060  /* Check parameters */
3061  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
3062  assert_param(Channel != NULL);
3063 
3064  /* Get value of data register for injected channel */
3065  reg = hdfsdm_filter->Instance->FLTJDATAR;
3066 
3067  /* Extract channel and injected conversion value */
3068  *Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
3069  value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_JDATA_Pos);
3070 
3071  /* return regular conversion value */
3072  return value;
3073 }
3074 
3081 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
3082  const DFSDM_Filter_AwdParamTypeDef *awdParam)
3083 {
3084  HAL_StatusTypeDef status = HAL_OK;
3085 
3086  /* Check parameters */
3087  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
3088  assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));
3089  assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));
3090  assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));
3091  assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));
3092  assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));
3093  assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));
3094 
3095  /* Check DFSDM filter state */
3096  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
3097  (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
3098  {
3099  /* Return error status */
3100  status = HAL_ERROR;
3101  }
3102  else
3103  {
3104  /* Set analog watchdog data source */
3105  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
3106  hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;
3107 
3108  /* Set thresholds and break signals */
3109  hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
3110  hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \
3111  awdParam->HighBreakSignal);
3112  hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
3113  hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \
3114  awdParam->LowBreakSignal);
3115 
3116  /* Set channels and interrupt for analog watchdog */
3117  hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);
3118  hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_Pos) | \
3119  DFSDM_FLTCR2_AWDIE);
3120  }
3121  /* Return function status */
3122  return status;
3123 }
3124 
3130 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3131 {
3132  HAL_StatusTypeDef status = HAL_OK;
3133 
3134  /* Check parameters */
3135  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
3136 
3137  /* Check DFSDM filter state */
3138  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
3139  (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
3140  {
3141  /* Return error status */
3142  status = HAL_ERROR;
3143  }
3144  else
3145  {
3146  /* Reset channels for analog watchdog and deactivate interrupt */
3147  hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);
3148 
3149  /* Clear all analog watchdog flags */
3150  hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);
3151 
3152  /* Reset thresholds and break signals */
3153  hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
3154  hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
3155 
3156  /* Reset analog watchdog data source */
3157  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
3158  }
3159  /* Return function status */
3160  return status;
3161 }
3162 
3170 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
3171  uint32_t Channel)
3172 {
3173  HAL_StatusTypeDef status = HAL_OK;
3174 
3175  /* Check parameters */
3176  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
3177  assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
3178 
3179  /* Check DFSDM filter state */
3180  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
3181  (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
3182  {
3183  /* Return error status */
3184  status = HAL_ERROR;
3185  }
3186  else
3187  {
3188  /* Set channels for extreme detector */
3189  hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
3190  hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos);
3191  }
3192  /* Return function status */
3193  return status;
3194 }
3195 
3201 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3202 {
3203  HAL_StatusTypeDef status = HAL_OK;
3204  __IO uint32_t reg1;
3205  __IO uint32_t reg2;
3206 
3207  /* Check parameters */
3208  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
3209 
3210  /* Check DFSDM filter state */
3211  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
3212  (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
3213  {
3214  /* Return error status */
3215  status = HAL_ERROR;
3216  }
3217  else
3218  {
3219  /* Reset channels for extreme detector */
3220  hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
3221 
3222  /* Clear extreme detector values */
3223  reg1 = hdfsdm_filter->Instance->FLTEXMAX;
3224  reg2 = hdfsdm_filter->Instance->FLTEXMIN;
3225  UNUSED(reg1); /* To avoid GCC warning */
3226  UNUSED(reg2); /* To avoid GCC warning */
3227  }
3228  /* Return function status */
3229  return status;
3230 }
3231 
3239 int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
3240  uint32_t *Channel)
3241 {
3242  uint32_t reg = 0U;
3243  int32_t value = 0;
3244 
3245  /* Check parameters */
3246  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
3247  assert_param(Channel != NULL);
3248 
3249  /* Get value of extreme detector maximum register */
3250  reg = hdfsdm_filter->Instance->FLTEXMAX;
3251 
3252  /* Extract channel and extreme detector maximum value */
3253  *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
3254  value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_EXMAX_Pos);
3255 
3256  /* return extreme detector maximum value */
3257  return value;
3258 }
3259 
3267 int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
3268  uint32_t *Channel)
3269 {
3270  uint32_t reg = 0U;
3271  int32_t value = 0;
3272 
3273  /* Check parameters */
3274  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
3275  assert_param(Channel != NULL);
3276 
3277  /* Get value of extreme detector minimum register */
3278  reg = hdfsdm_filter->Instance->FLTEXMIN;
3279 
3280  /* Extract channel and extreme detector minimum value */
3281  *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
3282  value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_EXMIN_Pos);
3283 
3284  /* return extreme detector minimum value */
3285  return value;
3286 }
3287 
3294 uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3295 {
3296  uint32_t reg = 0U;
3297  uint32_t value = 0U;
3298 
3299  /* Check parameters */
3300  assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
3301 
3302  /* Get value of conversion timer register */
3303  reg = hdfsdm_filter->Instance->FLTCNVTIMR;
3304 
3305  /* Extract conversion time value */
3306  value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos);
3307 
3308  /* return extreme detector minimum value */
3309  return value;
3310 }
3311 
3317 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3318 {
3319  /* Check if overrun occurs during regular conversion */
3320  if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0U) && \
3321  ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0U))
3322  {
3323  /* Clear regular overrun flag */
3324  hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
3325 
3326  /* Update error code */
3327  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
3328 
3329  /* Call error callback */
3330 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3331  hdfsdm_filter->ErrorCallback(hdfsdm_filter);
3332 #else
3333  HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
3334 #endif
3335  }
3336  /* Check if overrun occurs during injected conversion */
3337  else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0U) && \
3338  ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0U))
3339  {
3340  /* Clear injected overrun flag */
3341  hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
3342 
3343  /* Update error code */
3344  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
3345 
3346  /* Call error callback */
3347 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3348  hdfsdm_filter->ErrorCallback(hdfsdm_filter);
3349 #else
3350  HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
3351 #endif
3352  }
3353  /* Check if end of regular conversion */
3354  else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0U) && \
3355  ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0U))
3356  {
3357  /* Call regular conversion complete callback */
3358 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3359  hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);
3360 #else
3361  HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
3362 #endif
3363 
3364  /* End of conversion if mode is not continuous and software trigger */
3365  if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
3366  (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
3367  {
3368  /* Disable interrupts for regular conversions */
3369  hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);
3370 
3371  /* Update DFSDM filter state */
3372  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
3373  HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
3374  }
3375  }
3376  /* Check if end of injected conversion */
3377  else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0U) && \
3378  ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0U))
3379  {
3380  /* Call injected conversion complete callback */
3381 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3382  hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);
3383 #else
3384  HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
3385 #endif
3386 
3387  /* Update remaining injected conversions */
3388  hdfsdm_filter->InjConvRemaining--;
3389  if(hdfsdm_filter->InjConvRemaining == 0U)
3390  {
3391  /* End of conversion if trigger is software */
3392  if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
3393  {
3394  /* Disable interrupts for injected conversions */
3395  hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);
3396 
3397  /* Update DFSDM filter state */
3398  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
3399  HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
3400  }
3401  /* end of injected sequence, reset the value */
3402  hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
3403  hdfsdm_filter->InjectedChannelsNbr : 1U;
3404  }
3405  }
3406  /* Check if analog watchdog occurs */
3407  else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0U) && \
3408  ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0U))
3409  {
3410  uint32_t reg = 0U;
3411  uint32_t threshold = 0U;
3412  uint32_t channel = 0U;
3413 
3414  /* Get channel and threshold */
3415  reg = hdfsdm_filter->Instance->FLTAWSR;
3416  threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
3417  if(threshold == DFSDM_AWD_HIGH_THRESHOLD)
3418  {
3419  reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos;
3420  }
3421  while((reg & 1U) == 0U)
3422  {
3423  channel++;
3424  reg = reg >> 1U;
3425  }
3426  /* Clear analog watchdog flag */
3427  hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \
3428  (1U << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \
3429  (1U << channel);
3430 
3431  /* Call analog watchdog callback */
3432 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3433  hdfsdm_filter->AwdCallback(hdfsdm_filter, channel, threshold);
3434 #else
3435  HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
3436 #endif
3437  }
3438  /* Check if clock absence occurs */
3439  else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
3440  ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0U) && \
3441  ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0U))
3442  {
3443  uint32_t reg = 0U;
3444  uint32_t channel = 0U;
3445 
3446  reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);
3447 
3448  while(channel < DFSDM1_CHANNEL_NUMBER)
3449  {
3450  /* Check if flag is set and corresponding channel is enabled */
3451  if(((reg & 1U) != 0U) && (a_dfsdm1ChannelHandle[channel] != NULL))
3452  {
3453  /* Check clock absence has been enabled for this channel */
3454  if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U)
3455  {
3456  /* Clear clock absence flag */
3457  hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
3458 
3459  /* Call clock absence callback */
3460 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3461  a_dfsdm1ChannelHandle[channel]->CkabCallback(a_dfsdm1ChannelHandle[channel]);
3462 #else
3463  HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
3464 #endif
3465  }
3466  }
3467  channel++;
3468  reg = reg >> 1U;
3469  }
3470  }
3471 #if defined (DFSDM2_Channel0)
3472  /* Check if clock absence occurs */
3473  else if((hdfsdm_filter->Instance == DFSDM2_Filter0) && \
3474  ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0U) && \
3475  ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0U))
3476  {
3477  uint32_t reg = 0U;
3478  uint32_t channel = 0U;
3479 
3480  reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);
3481 
3482  while(channel < DFSDM2_CHANNEL_NUMBER)
3483  {
3484  /* Check if flag is set and corresponding channel is enabled */
3485  if(((reg & 1U) != 0U) && (a_dfsdm2ChannelHandle[channel] != NULL))
3486  {
3487  /* Check clock absence has been enabled for this channel */
3488  if((a_dfsdm2ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U)
3489  {
3490  /* Clear clock absence flag */
3491  hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
3492 
3493  /* Call clock absence callback */
3494 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3495  a_dfsdm2ChannelHandle[channel]->CkabCallback(a_dfsdm2ChannelHandle[channel]);
3496 #else
3497  HAL_DFSDM_ChannelCkabCallback(a_dfsdm2ChannelHandle[channel]);
3498 #endif
3499  }
3500  }
3501  channel++;
3502  reg = reg >> 1U;
3503  }
3504  }
3505 #endif /* DFSDM2_Channel0 */
3506  /* Check if short circuit detection occurs */
3507  else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
3508  ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \
3509  ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0U))
3510  {
3511  uint32_t reg = 0U;
3512  uint32_t channel = 0U;
3513 
3514  /* Get channel */
3515  reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);
3516  while((reg & 1U) == 0U)
3517  {
3518  channel++;
3519  reg = reg >> 1U;
3520  }
3521 
3522  /* Clear short circuit detection flag */
3523  hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
3524 
3525  /* Call short circuit detection callback */
3526 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3527  a_dfsdm1ChannelHandle[channel]->ScdCallback(a_dfsdm1ChannelHandle[channel]);
3528 #else
3529  HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
3530 #endif
3531  }
3532 #if defined (DFSDM2_Channel0)
3533  /* Check if short circuit detection occurs */
3534  else if((hdfsdm_filter->Instance == DFSDM2_Filter0) && \
3535  ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \
3536  ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0U))
3537  {
3538  uint32_t reg = 0U;
3539  uint32_t channel = 0U;
3540 
3541  /* Get channel */
3542  reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);
3543  while((reg & 1U) == 0U)
3544  {
3545  channel++;
3546  reg = reg >> 1U;
3547  }
3548 
3549  /* Clear short circuit detection flag */
3550  hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
3551 
3552  /* Call short circuit detection callback */
3553 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
3554  a_dfsdm2ChannelHandle[channel]->ScdCallback(a_dfsdm2ChannelHandle[channel]);
3555 #else
3556  HAL_DFSDM_ChannelScdCallback(a_dfsdm2ChannelHandle[channel]);
3557 #endif
3558  }
3559 #endif /* DFSDM2_Channel0 */
3560 }
3561 
3569 __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3570 {
3571  /* Prevent unused argument(s) compilation warning */
3572  UNUSED(hdfsdm_filter);
3573  /* NOTE : This function should not be modified, when the callback is needed,
3574  the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file.
3575  */
3576 }
3577 
3583 __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3584 {
3585  /* Prevent unused argument(s) compilation warning */
3586  UNUSED(hdfsdm_filter);
3587  /* NOTE : This function should not be modified, when the callback is needed,
3588  the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file.
3589  */
3590 }
3591 
3599 __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3600 {
3601  /* Prevent unused argument(s) compilation warning */
3602  UNUSED(hdfsdm_filter);
3603  /* NOTE : This function should not be modified, when the callback is needed,
3604  the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file.
3605  */
3606 }
3607 
3613 __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3614 {
3615  /* Prevent unused argument(s) compilation warning */
3616  UNUSED(hdfsdm_filter);
3617  /* NOTE : This function should not be modified, when the callback is needed,
3618  the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file.
3619  */
3620 }
3621 
3629 __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
3630  uint32_t Channel, uint32_t Threshold)
3631 {
3632  /* Prevent unused argument(s) compilation warning */
3633  UNUSED(hdfsdm_filter);
3634  UNUSED(Channel);
3635  UNUSED(Threshold);
3636 
3637  /* NOTE : This function should not be modified, when the callback is needed,
3638  the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.
3639  */
3640 }
3641 
3647 __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3648 {
3649  /* Prevent unused argument(s) compilation warning */
3650  UNUSED(hdfsdm_filter);
3651  /* NOTE : This function should not be modified, when the callback is needed,
3652  the HAL_DFSDM_FilterErrorCallback could be implemented in the user file.
3653  */
3654 }
3655 
3679 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3680 {
3681  /* Return DFSDM filter handle state */
3682  return hdfsdm_filter->State;
3683 }
3684 
3690 uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3691 {
3692  return hdfsdm_filter->ErrorCode;
3693 }
3694 
3711 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)
3717 void HAL_DFSDM_BitstreamClock_Start(void)
3718 {
3719  uint32_t tmp = 0;
3720 
3721  tmp = SYSCFG->MCHDLYCR;
3722  tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL));
3723 
3724  SYSCFG->MCHDLYCR = (tmp|SYSCFG_MCHDLYCR_BSCKSEL);
3725 }
3726 
3733 void HAL_DFSDM_BitstreamClock_Stop(void)
3734 {
3735  uint32_t tmp = 0U;
3736 
3737  tmp = SYSCFG->MCHDLYCR;
3738  tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL));
3739 
3740  SYSCFG->MCHDLYCR = tmp;
3741 }
3742 
3751 void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY)
3752 {
3753  uint32_t tmp = 0U;
3754 
3755  assert_param(IS_DFSDM_DELAY_CLOCK(MCHDLY));
3756 
3757  tmp = SYSCFG->MCHDLYCR;
3758  if(MCHDLY == HAL_MCHDLY_CLOCK_DFSDM2)
3759  {
3760  tmp = tmp &(~SYSCFG_MCHDLYCR_MCHDLY2EN);
3761  }
3762  else
3763  {
3764  tmp = tmp &(~SYSCFG_MCHDLYCR_MCHDLY1EN);
3765  }
3766 
3767  SYSCFG->MCHDLYCR = tmp;
3768 }
3769 
3778 void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY)
3779 {
3780  uint32_t tmp = 0U;
3781 
3782  assert_param(IS_DFSDM_DELAY_CLOCK(MCHDLY));
3783 
3784  tmp = SYSCFG->MCHDLYCR;
3785  tmp = tmp & ~MCHDLY;
3786 
3787  SYSCFG->MCHDLYCR = (tmp|MCHDLY);
3788 }
3789 
3798 void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source)
3799 {
3800  uint32_t tmp = 0U;
3801 
3802  assert_param(IS_DFSDM_CLOCKIN_SELECTION(source));
3803 
3804  tmp = SYSCFG->MCHDLYCR;
3805 
3806  if((source == HAL_DFSDM2_CKIN_PAD) || (source == HAL_DFSDM2_CKIN_DM))
3807  {
3808  tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CFG);
3809 
3810  if(source == HAL_DFSDM2_CKIN_PAD)
3811  {
3812  source = 0x000000U;
3813  }
3814  }
3815  else
3816  {
3817  tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CFG);
3818  }
3819 
3820  SYSCFG->MCHDLYCR = (source|tmp);
3821 }
3822 
3831 void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source)
3832 {
3833  uint32_t tmp = 0U;
3834 
3835  assert_param(IS_DFSDM_CLOCKOUT_SELECTION(source));
3836 
3837  tmp = SYSCFG->MCHDLYCR;
3838 
3839  if((source == HAL_DFSDM2_CKOUT_DFSDM2) || (source == HAL_DFSDM2_CKOUT_M27))
3840  {
3841  tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CKOSEL);
3842 
3843  if(source == HAL_DFSDM2_CKOUT_DFSDM2)
3844  {
3845  source = 0x000U;
3846  }
3847  }
3848  else
3849  {
3850  tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CKOSEL);
3851  }
3852 
3853  SYSCFG->MCHDLYCR = (source|tmp);
3854 }
3855 
3864 void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source)
3865 {
3866  uint32_t tmp = 0U;
3867 
3868  assert_param(IS_DFSDM_DATAIN0_SRC_SELECTION(source));
3869 
3870  tmp = SYSCFG->MCHDLYCR;
3871 
3872  if((source == HAL_DATAIN0_DFSDM2_PAD)|| (source == HAL_DATAIN0_DFSDM2_DATAIN1))
3873  {
3874  tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D0SEL);
3875  if(source == HAL_DATAIN0_DFSDM2_PAD)
3876  {
3877  source = 0x00000U;
3878  }
3879  }
3880  else
3881  {
3882  tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1D0SEL);
3883  }
3884  SYSCFG->MCHDLYCR = (source|tmp);
3885 }
3886 
3895 void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source)
3896 {
3897  uint32_t tmp = 0U;
3898 
3899  assert_param(IS_DFSDM_DATAIN2_SRC_SELECTION(source));
3900 
3901  tmp = SYSCFG->MCHDLYCR;
3902 
3903  if((source == HAL_DATAIN2_DFSDM2_PAD)|| (source == HAL_DATAIN2_DFSDM2_DATAIN3))
3904  {
3905  tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D2SEL);
3906  if (source == HAL_DATAIN2_DFSDM2_PAD)
3907  {
3908  source = 0x0000U;
3909  }
3910  }
3911  else
3912  {
3913  tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1D2SEL);
3914  }
3915  SYSCFG->MCHDLYCR = (source|tmp);
3916 }
3917 
3924 void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source)
3925 {
3926  uint32_t tmp = 0U;
3927 
3928  assert_param(IS_DFSDM_DATAIN4_SRC_SELECTION(source));
3929 
3930  tmp = SYSCFG->MCHDLYCR;
3931  tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D4SEL);
3932 
3933  SYSCFG->MCHDLYCR = (source|tmp);
3934 }
3935 
3942 void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source)
3943 {
3944  uint32_t tmp = 0U;
3945 
3946  assert_param(IS_DFSDM_DATAIN6_SRC_SELECTION(source));
3947 
3948  tmp = SYSCFG->MCHDLYCR;
3949 
3950  tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D6SEL);
3951 
3952  SYSCFG->MCHDLYCR = (source|tmp);
3953 }
3954 
3972 void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source)
3973 {
3974  uint32_t tmp = 0U;
3975 
3976  assert_param(IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(source));
3977 
3978  tmp = SYSCFG->MCHDLYCR;
3979 
3980  if ((source == HAL_DFSDM1_CLKIN0_TIM4OC2) || (source == HAL_DFSDM1_CLKIN2_TIM4OC2))
3981  {
3982  tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CK02SEL);
3983  }
3984  else if ((source == HAL_DFSDM1_CLKIN1_TIM4OC1) || (source == HAL_DFSDM1_CLKIN3_TIM4OC1))
3985  {
3986  tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CK13SEL);
3987  }
3988  else if ((source == HAL_DFSDM2_CLKIN0_TIM3OC4) || (source == HAL_DFSDM2_CLKIN4_TIM3OC4))
3989  {
3990  tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK04SEL);
3991  }
3992  else if ((source == HAL_DFSDM2_CLKIN1_TIM3OC3) || (source == HAL_DFSDM2_CLKIN5_TIM3OC3))
3993  {
3994  tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK15SEL);
3995 
3996  }else if ((source == HAL_DFSDM2_CLKIN2_TIM3OC2) || (source == HAL_DFSDM2_CLKIN6_TIM3OC2))
3997  {
3998  tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK26SEL);
3999  }
4000  else
4001  {
4002  tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK37SEL);
4003  }
4004 
4005  if((source == HAL_DFSDM1_CLKIN0_TIM4OC2) ||(source == HAL_DFSDM1_CLKIN1_TIM4OC1)||
4006  (source == HAL_DFSDM2_CLKIN0_TIM3OC4) ||(source == HAL_DFSDM2_CLKIN1_TIM3OC3)||
4007  (source == HAL_DFSDM2_CLKIN2_TIM3OC2) ||(source == HAL_DFSDM2_CLKIN3_TIM3OC1))
4008  {
4009  source = 0x0000U;
4010  }
4011 
4012  SYSCFG->MCHDLYCR = (source|tmp);
4013 }
4014 
4030 void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct)
4031 {
4032  uint32_t mchdlyreg = 0U;
4033 
4034  assert_param(IS_DFSDM_DFSDM1_CLKOUT(mchdlystruct->DFSDM1ClockOut));
4035  assert_param(IS_DFSDM_DFSDM2_CLKOUT(mchdlystruct->DFSDM2ClockOut));
4036  assert_param(IS_DFSDM_DFSDM1_CLKIN(mchdlystruct->DFSDM1ClockIn));
4037  assert_param(IS_DFSDM_DFSDM2_CLKIN(mchdlystruct->DFSDM2ClockIn));
4038  assert_param(IS_DFSDM_DFSDM1_BIT_CLK((mchdlystruct->DFSDM1BitClkDistribution)));
4039  assert_param(IS_DFSDM_DFSDM2_BIT_CLK(mchdlystruct->DFSDM2BitClkDistribution));
4040  assert_param(IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(mchdlystruct->DFSDM1DataDistribution));
4041  assert_param(IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(mchdlystruct->DFSDM2DataDistribution));
4042 
4043  mchdlyreg = (SYSCFG->MCHDLYCR & 0x80103U);
4044 
4045  SYSCFG->MCHDLYCR = (mchdlyreg |(mchdlystruct->DFSDM1ClockOut)|(mchdlystruct->DFSDM2ClockOut)|
4046  (mchdlystruct->DFSDM1ClockIn)|(mchdlystruct->DFSDM2ClockIn)|
4047  (mchdlystruct->DFSDM1BitClkDistribution)| (mchdlystruct->DFSDM2BitClkDistribution)|
4048  (mchdlystruct->DFSDM1DataDistribution)| (mchdlystruct->DFSDM2DataDistribution));
4049 
4050 }
4051 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */
4058 /* End of exported functions -------------------------------------------------*/
4059 
4060 /* Private functions ---------------------------------------------------------*/
4070 static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
4071 {
4072  /* Get DFSDM filter handle */
4073  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
4074 
4075  /* Call regular half conversion complete callback */
4076 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
4077  hdfsdm_filter->RegConvHalfCpltCallback(hdfsdm_filter);
4078 #else
4079  HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
4080 #endif
4081 }
4082 
4088 static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
4089 {
4090  /* Get DFSDM filter handle */
4091  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
4092 
4093  /* Call regular conversion complete callback */
4094 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
4095  hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);
4096 #else
4097  HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
4098 #endif
4099 }
4100 
4106 static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
4107 {
4108  /* Get DFSDM filter handle */
4109  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
4110 
4111  /* Call injected half conversion complete callback */
4112 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
4113  hdfsdm_filter->InjConvHalfCpltCallback(hdfsdm_filter);
4114 #else
4115  HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
4116 #endif
4117 }
4118 
4124 static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
4125 {
4126  /* Get DFSDM filter handle */
4127  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
4128 
4129  /* Call injected conversion complete callback */
4130 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
4131  hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);
4132 #else
4133  HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
4134 #endif
4135 }
4136 
4142 static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
4143 {
4144  /* Get DFSDM filter handle */
4145  DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
4146 
4147  /* Update error code */
4148  hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
4149 
4150  /* Call error callback */
4151 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
4152  hdfsdm_filter->ErrorCallback(hdfsdm_filter);
4153 #else
4154  HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
4155 #endif
4156 }
4157 
4163 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
4164 {
4165  uint32_t nbChannels = 0U;
4166  uint32_t tmp;
4167 
4168  /* Get the number of channels from bitfield */
4169  tmp = (uint32_t) (Channels & DFSDM_LSB_MASK);
4170  while(tmp != 0U)
4171  {
4172  if((tmp & 1U) != 0U)
4173  {
4174  nbChannels++;
4175  }
4176  tmp = (uint32_t) (tmp >> 1U);
4177  }
4178  return nbChannels;
4179 }
4180 
4186 static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance)
4187 {
4188  uint32_t channel;
4189 
4190  /* Get channel from instance */
4191 #if defined(DFSDM2_Channel0)
4192  if((Instance == DFSDM1_Channel0) || (Instance == DFSDM2_Channel0))
4193  {
4194  channel = 0U;
4195  }
4196  else if((Instance == DFSDM1_Channel1) || (Instance == DFSDM2_Channel1))
4197  {
4198  channel = 1U;
4199  }
4200  else if((Instance == DFSDM1_Channel2) || (Instance == DFSDM2_Channel2))
4201  {
4202  channel = 2U;
4203  }
4204  else if((Instance == DFSDM1_Channel3) || (Instance == DFSDM2_Channel3))
4205  {
4206  channel = 3U;
4207  }
4208  else if(Instance == DFSDM2_Channel4)
4209  {
4210  channel = 4U;
4211  }
4212  else if(Instance == DFSDM2_Channel5)
4213  {
4214  channel = 5U;
4215  }
4216  else if(Instance == DFSDM2_Channel6)
4217  {
4218  channel = 6U;
4219  }
4220  else /* DFSDM2_Channel7 */
4221  {
4222  channel = 7U;
4223  }
4224 
4225 #else
4226  if(Instance == DFSDM1_Channel0)
4227  {
4228  channel = 0U;
4229  }
4230  else if(Instance == DFSDM1_Channel1)
4231  {
4232  channel = 1U;
4233  }
4234  else if(Instance == DFSDM1_Channel2)
4235  {
4236  channel = 2U;
4237  }
4238  else /* DFSDM1_Channel3 */
4239  {
4240  channel = 3U;
4241  }
4242 #endif /* defined(DFSDM2_Channel0) */
4243 
4244  return channel;
4245 }
4246 
4252 static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
4253 {
4254  /* Check regular trigger */
4255  if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)
4256  {
4257  /* Software start of regular conversion */
4258  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
4259  }
4260  else /* synchronous trigger */
4261  {
4262  /* Disable DFSDM filter */
4263  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
4264 
4265  /* Set RSYNC bit in DFSDM_FLTCR1 register */
4266  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
4267 
4268  /* Enable DFSDM filter */
4269  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
4270 
4271  /* If injected conversion was in progress, restart it */
4272  if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)
4273  {
4274  if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
4275  {
4276  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
4277  }
4278  /* Update remaining injected conversions */
4279  hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
4280  hdfsdm_filter->InjectedChannelsNbr : 1U;
4281  }
4282  }
4283  /* Update DFSDM filter state */
4284  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
4285  HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;
4286 }
4287 
4293 static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
4294 {
4295  /* Disable DFSDM filter */
4296  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
4297 
4298  /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */
4299  if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)
4300  {
4301  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
4302  }
4303 
4304  /* Enable DFSDM filter */
4305  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
4306 
4307  /* If injected conversion was in progress, restart it */
4308  if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)
4309  {
4310  if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
4311  {
4312  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
4313  }
4314  /* Update remaining injected conversions */
4315  hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
4316  hdfsdm_filter->InjectedChannelsNbr : 1U;
4317  }
4318 
4319  /* Update DFSDM filter state */
4320  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
4321  HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
4322 }
4323 
4329 static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
4330 {
4331  /* Check injected trigger */
4332  if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
4333  {
4334  /* Software start of injected conversion */
4335  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
4336  }
4337  else /* external or synchronous trigger */
4338  {
4339  /* Disable DFSDM filter */
4340  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
4341 
4342  if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
4343  {
4344  /* Set JSYNC bit in DFSDM_FLTCR1 register */
4345  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;
4346  }
4347  else /* external trigger */
4348  {
4349  /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
4350  hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;
4351  }
4352 
4353  /* Enable DFSDM filter */
4354  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
4355 
4356  /* If regular conversion was in progress, restart it */
4357  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \
4358  (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
4359  {
4360  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
4361  }
4362  }
4363  /* Update DFSDM filter state */
4364  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
4365  HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;
4366 }
4367 
4373 static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
4374 {
4375  /* Disable DFSDM filter */
4376  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
4377 
4378  /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */
4379  if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
4380  {
4381  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);
4382  }
4383  else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)
4384  {
4385  /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
4386  hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);
4387  }
4388 
4389  else
4390  {
4391  /* Nothing to do */
4392  }
4393  /* Enable DFSDM filter */
4394  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
4395 
4396  /* If regular conversion was in progress, restart it */
4397  if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \
4398  (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
4399  {
4400  hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
4401  }
4402 
4403  /* Update remaining injected conversions */
4404  hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
4405  hdfsdm_filter->InjectedChannelsNbr : 1U;
4406 
4407  /* Update DFSDM filter state */
4408  hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
4409  HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
4410 }
4414 /* End of private functions --------------------------------------------------*/
4415 
4419 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
4420 #endif /* HAL_DFSDM_MODULE_ENABLED */
HAL_DFSDM_ChannelDeInit
HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel.
Definition: stm32f4xx_hal_dfsdm.c:575
HAL_DFSDM_Channel_RegisterCallback
HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, pDFSDM_Channel_CallbackTypeDef pCallback)
Register a user DFSDM channel callback to be used instead of the weak predefined callback.
Definition: stm32f4xx_hal_dfsdm.c:723
HAL_DFSDM_Channel_UnRegisterCallback
HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID)
Unregister a user DFSDM channel callback. DFSDM channel callback is redirected to the weak predefined...
Definition: stm32f4xx_hal_dfsdm.c:795
HAL_DFSDM_ChannelMspDeInit
void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
De-initialize the DFSDM channel MSP.
Definition: stm32f4xx_hal_dfsdm.c:700
HAL_DFSDM_ChannelMspInit
void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel MSP.
Definition: stm32f4xx_hal_dfsdm.c:686
HAL_DFSDM_ChannelInit
HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Initialize the DFSDM channel according to the specified parameters in the DFSDM_ChannelInitTypeDef st...
Definition: stm32f4xx_hal_dfsdm.c:367
HAL_DFSDM_FilterMspInit
void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initializes the DFSDM filter MSP.
Definition: stm32f4xx_hal_dfsdm.c:1859
HAL_DFSDM_Filter_RegisterAwdCallback
HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, pDFSDM_Filter_AwdCallbackTypeDef pCallback)
Register a user DFSDM filter analog watchdog callback to be used instead of the weak predefined callb...
Definition: stm32f4xx_hal_dfsdm.c:2064
HAL_DFSDM_Filter_UnRegisterCallback
HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID)
Unregister a user DFSDM filter callback. DFSDM filter callback is redirected to the weak predefined c...
Definition: stm32f4xx_hal_dfsdm.c:1991
HAL_DFSDM_FilterMspDeInit
void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter MSP.
Definition: stm32f4xx_hal_dfsdm.c:1873
HAL_DFSDM_Filter_RegisterCallback
HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, pDFSDM_Filter_CallbackTypeDef pCallback)
Register a user DFSDM filter callback to be used instead of the weak predefined callback.
Definition: stm32f4xx_hal_dfsdm.c:1899
HAL_DFSDM_FilterInit
HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Initialize the DFSDM filter according to the specified parameters in the DFSDM_FilterInitTypeDef stru...
Definition: stm32f4xx_hal_dfsdm.c:1688
HAL_DFSDM_FilterDeInit
HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
De-initializes the DFSDM filter.
Definition: stm32f4xx_hal_dfsdm.c:1823
HAL_DFSDM_Filter_UnRegisterAwdCallback
HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Unregister a user DFSDM filter analog watchdog callback. DFSDM filter AWD callback is redirected to t...
Definition: stm32f4xx_hal_dfsdm.c:2099
HAL_DFSDM_ChannelScdStart
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in polling mode.
Definition: stm32f4xx_hal_dfsdm.c:1295
HAL_DFSDM_ChannelScdStart_IT
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal)
This function allows to start short circuit detection in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:1473
HAL_DFSDM_ChannelCkabStart
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in polling mode.
Definition: stm32f4xx_hal_dfsdm.c:875
HAL_DFSDM_ChannelCkabCallback
void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Clock absence detection callback.
Definition: stm32f4xx_hal_dfsdm.c:1212
HAL_DFSDM_ChannelCkabStop_IT
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:1227
HAL_DFSDM_ChannelGetAwdValue
int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get channel analog watchdog value.
Definition: stm32f4xx_hal_dfsdm.c:1599
HAL_DFSDM_ChannelPollForScd
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the short circuit detection.
Definition: stm32f4xx_hal_dfsdm.c:1332
HAL_DFSDM_ChannelScdStop
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in polling mode.
Definition: stm32f4xx_hal_dfsdm.c:1418
HAL_DFSDM_ChannelPollForCkab
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout)
This function allows to poll for the clock absence detection.
Definition: stm32f4xx_hal_dfsdm.c:963
HAL_DFSDM_ChannelModifyOffset
HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset)
This function allows to modify channel offset value.
Definition: stm32f4xx_hal_dfsdm.c:1611
HAL_DFSDM_ChannelScdCallback
void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
Short circuit detection callback.
Definition: stm32f4xx_hal_dfsdm.c:1529
HAL_DFSDM_ChannelCkabStart_IT
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to start clock absence detection in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:1111
HAL_DFSDM_ChannelCkabStop
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop clock absence detection in polling mode.
Definition: stm32f4xx_hal_dfsdm.c:1051
HAL_DFSDM_ChannelScdStop_IT
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to stop short circuit detection in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:1544
HAL_DFSDM_FilterConfigRegChannel
HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t ContinuousMode)
This function allows to select channel and to enable/disable continuous mode for regular conversion.
Definition: stm32f4xx_hal_dfsdm.c:2145
HAL_DFSDM_FilterConfigInjChannel
HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to select channels for injected conversion.
Definition: stm32f4xx_hal_dfsdm.c:2190
HAL_DFSDM_ChannelGetState
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
This function allows to get the current DFSDM channel handle state.
Definition: stm32f4xx_hal_dfsdm.c:1658
HAL_DFSDM_FilterRegConvCpltCallback
void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Regular conversion complete callback.
Definition: stm32f4xx_hal_dfsdm.c:3569
HAL_DFSDM_FilterRegularStart
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in polling mode.
Definition: stm32f4xx_hal_dfsdm.c:2260
HAL_DFSDM_FilterGetInjectedValue
int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get injected conversion value.
Definition: stm32f4xx_hal_dfsdm.c:3054
HAL_DFSDM_FilterRegularStop_IT
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:2415
HAL_DFSDM_FilterInjectedStart_DMA
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode.
Definition: stm32f4xx_hal_dfsdm.c:2871
HAL_DFSDM_IRQHandler
void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function handles the DFSDM interrupts.
Definition: stm32f4xx_hal_dfsdm.c:3317
HAL_DFSDM_FilterInjConvCpltCallback
void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Injected conversion complete callback.
Definition: stm32f4xx_hal_dfsdm.c:3599
HAL_DFSDM_FilterGetExdMinValue
int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector minimum value.
Definition: stm32f4xx_hal_dfsdm.c:3267
HAL_DFSDM_FilterExdStop
HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop extreme detector feature.
Definition: stm32f4xx_hal_dfsdm.c:3201
HAL_DFSDM_FilterAwdCallback
void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold)
Filter analog watchdog callback.
Definition: stm32f4xx_hal_dfsdm.c:3629
HAL_DFSDM_FilterRegularMsbStart_DMA
HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode and to get only the 16 most significant ...
Definition: stm32f4xx_hal_dfsdm.c:2530
HAL_DFSDM_FilterPollForRegConversion
HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of regular conversion.
Definition: stm32f4xx_hal_dfsdm.c:2289
HAL_DFSDM_FilterInjectedMsbStart_DMA
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length)
This function allows to start injected conversion in DMA mode and to get only the 16 most significant...
Definition: stm32f4xx_hal_dfsdm.c:2946
HAL_DFSDM_FilterAwdStop_IT
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop filter analog watchdog in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:3130
HAL_DFSDM_FilterRegularStart_DMA
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length)
This function allows to start regular conversion in DMA mode.
Definition: stm32f4xx_hal_dfsdm.c:2453
HAL_DFSDM_FilterGetExdMaxValue
int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get extreme detector maximum value.
Definition: stm32f4xx_hal_dfsdm.c:3239
HAL_DFSDM_FilterErrorCallback
void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Error callback.
Definition: stm32f4xx_hal_dfsdm.c:3647
HAL_DFSDM_FilterInjectedStop_DMA
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in DMA mode.
Definition: stm32f4xx_hal_dfsdm.c:3015
HAL_DFSDM_FilterRegularStop
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in polling mode.
Definition: stm32f4xx_hal_dfsdm.c:2354
HAL_DFSDM_FilterRegularStop_DMA
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop regular conversion in DMA mode.
Definition: stm32f4xx_hal_dfsdm.c:2601
HAL_DFSDM_FilterPollForInjConversion
HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout)
This function allows to poll for the end of injected conversion.
Definition: stm32f4xx_hal_dfsdm.c:2697
HAL_DFSDM_FilterInjectedStart_IT
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:2802
HAL_DFSDM_FilterInjectedStart
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start injected conversion in polling mode.
Definition: stm32f4xx_hal_dfsdm.c:2668
HAL_DFSDM_FilterInjectedStop_IT
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:2833
HAL_DFSDM_FilterExdStart
HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel)
This function allows to start extreme detector feature.
Definition: stm32f4xx_hal_dfsdm.c:3170
HAL_DFSDM_FilterGetRegularValue
int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel)
This function allows to get regular conversion value.
Definition: stm32f4xx_hal_dfsdm.c:2640
HAL_DFSDM_FilterInjectedStop
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to stop injected conversion in polling mode.
Definition: stm32f4xx_hal_dfsdm.c:2772
HAL_DFSDM_FilterRegConvHalfCpltCallback
void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half regular conversion complete callback.
Definition: stm32f4xx_hal_dfsdm.c:3583
HAL_DFSDM_FilterGetConvTimeValue
uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get conversion time value.
Definition: stm32f4xx_hal_dfsdm.c:3294
HAL_DFSDM_FilterAwdStart_IT
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, const DFSDM_Filter_AwdParamTypeDef *awdParam)
This function allows to start filter analog watchdog in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:3081
HAL_DFSDM_FilterRegularStart_IT
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to start regular conversion in interrupt mode.
Definition: stm32f4xx_hal_dfsdm.c:2384
HAL_DFSDM_FilterInjConvHalfCpltCallback
void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
Half injected conversion complete callback.
Definition: stm32f4xx_hal_dfsdm.c:3613
HAL_DFSDM_FilterGetState
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter handle state.
Definition: stm32f4xx_hal_dfsdm.c:3679
HAL_DFSDM_FilterGetError
uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
This function allows to get the current DFSDM filter error.
Definition: stm32f4xx_hal_dfsdm.c:3690
HAL_DFSDM_BitStreamClkDistribution_Config
void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source)
Configure the distribution of the bitstream clock gated from TIM4_OC for DFSDM1 or TIM3_OC for DFSDM2...
Definition: stm32f4xx_hal_dfsdm.c:3972
HAL_DFSDM_DataIn2_SourceSelection
void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source)
Select the source for DataIn2 signals for DFSDM1/2.
Definition: stm32f4xx_hal_dfsdm.c:3895
HAL_DFSDM_ClockOut_SourceSelection
void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source)
Select the source for CKOut signals for DFSDM1/2.
Definition: stm32f4xx_hal_dfsdm.c:3831
HAL_DFSDM_BitstreamClock_Start
void HAL_DFSDM_BitstreamClock_Start(void)
Select the DFSDM2 as clock source for the bitstream clock.
Definition: stm32f4xx_hal_dfsdm.c:3717
HAL_DFSDM_ClockIn_SourceSelection
void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source)
Select the source for CKin signals for DFSDM1/2.
Definition: stm32f4xx_hal_dfsdm.c:3798
HAL_DFSDM_EnableDelayClock
void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY)
Enable Delay Clock for DFSDM1/2.
Definition: stm32f4xx_hal_dfsdm.c:3778
HAL_DFSDM_DataIn0_SourceSelection
void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source)
Select the source for DataIn0 signals for DFSDM1/2.
Definition: stm32f4xx_hal_dfsdm.c:3864
HAL_DFSDM_DataIn4_SourceSelection
void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source)
Select the source for DataIn4 signals for DFSDM2.
Definition: stm32f4xx_hal_dfsdm.c:3924
HAL_DFSDM_DataIn6_SourceSelection
void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source)
Select the source for DataIn6 signals for DFSDM2.
Definition: stm32f4xx_hal_dfsdm.c:3942
HAL_DFSDM_ConfigMultiChannelDelay
void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef *mchdlystruct)
Configure multi channel delay block: Use DFSDM2 audio clock source as input clock for DFSDM1 and DFSD...
Definition: stm32f4xx_hal_dfsdm.c:4030
HAL_DFSDM_BitstreamClock_Stop
void HAL_DFSDM_BitstreamClock_Stop(void)
Stop the DFSDM2 as clock source for the bitstream clock.
Definition: stm32f4xx_hal_dfsdm.c:3733
HAL_DFSDM_DisableDelayClock
void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY)
Disable Delay Clock for DFSDM1/2.
Definition: stm32f4xx_hal_dfsdm.c:3751
HAL_DMA_Abort
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer.
Definition: stm32f4xx_hal_dma.c:513
HAL_DMA_Start_IT
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
Definition: stm32f4xx_hal_dma.c:451
HAL_GetTick
uint32_t HAL_GetTick(void)
Provides a tick value in millisecond.
Definition: stm32f4xx_hal.c:323
stm32f4xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
DFSDM_Filter_AwdParamTypeDef::LowThreshold
int32_t LowThreshold
Definition: stm32f4xx_hal_dfsdm.h:261
DFSDM_MultiChannelConfigTypeDef::DFSDM2DataDistribution
uint32_t DFSDM2DataDistribution
Definition: stm32f4xx_hal_dfsdm.h:320
HAL_DFSDM_Filter_CallbackIDTypeDef
HAL_DFSDM_Filter_CallbackIDTypeDef
DFSDM filter callback ID enumeration definition.
Definition: stm32f4xx_hal_dfsdm.h:274
HAL_DFSDM_FILTER_MSPINIT_CB_ID
@ HAL_DFSDM_FILTER_MSPINIT_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:280
HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID
@ HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:278
HAL_DFSDM_FILTER_MSPDEINIT_CB_ID
@ HAL_DFSDM_FILTER_MSPDEINIT_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:281
HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID
@ HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:276
HAL_DFSDM_FILTER_ERROR_CB_ID
@ HAL_DFSDM_FILTER_ERROR_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:279
HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID
@ HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:275
HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID
@ HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:277
DFSDM_Channel_HandleTypeDef
struct __DFSDM_Channel_HandleTypeDef else typedef struct endif DFSDM_Channel_HandleTypeDef
DFSDM channel handle structure definition.
DFSDM_Filter_AwdParamTypeDef::HighBreakSignal
uint32_t HighBreakSignal
Definition: stm32f4xx_hal_dfsdm.h:263
DFSDM_Filter_AwdParamTypeDef::HighThreshold
int32_t HighThreshold
Definition: stm32f4xx_hal_dfsdm.h:259
DFSDM_MultiChannelConfigTypeDef::DFSDM1BitClkDistribution
uint32_t DFSDM1BitClkDistribution
Definition: stm32f4xx_hal_dfsdm.h:308
pDFSDM_Channel_CallbackTypeDef
void(* pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
DFSDM channel callback pointer definition.
Definition: stm32f4xx_hal_dfsdm.h:151
DFSDM_MultiChannelConfigTypeDef::DFSDM2ClockIn
uint32_t DFSDM2ClockIn
Definition: stm32f4xx_hal_dfsdm.h:302
HAL_DFSDM_Filter_StateTypeDef
HAL_DFSDM_Filter_StateTypeDef
HAL DFSDM Filter states definition.
Definition: stm32f4xx_hal_dfsdm.h:157
HAL_DFSDM_FILTER_STATE_INJ
@ HAL_DFSDM_FILTER_STATE_INJ
Definition: stm32f4xx_hal_dfsdm.h:161
HAL_DFSDM_FILTER_STATE_ERROR
@ HAL_DFSDM_FILTER_STATE_ERROR
Definition: stm32f4xx_hal_dfsdm.h:163
HAL_DFSDM_FILTER_STATE_REG
@ HAL_DFSDM_FILTER_STATE_REG
Definition: stm32f4xx_hal_dfsdm.h:160
HAL_DFSDM_FILTER_STATE_REG_INJ
@ HAL_DFSDM_FILTER_STATE_REG_INJ
Definition: stm32f4xx_hal_dfsdm.h:162
HAL_DFSDM_FILTER_STATE_READY
@ HAL_DFSDM_FILTER_STATE_READY
Definition: stm32f4xx_hal_dfsdm.h:159
HAL_DFSDM_FILTER_STATE_RESET
@ HAL_DFSDM_FILTER_STATE_RESET
Definition: stm32f4xx_hal_dfsdm.h:158
pDFSDM_Filter_CallbackTypeDef
void(* pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
DFSDM filter callback pointer definition.
Definition: stm32f4xx_hal_dfsdm.h:287
DFSDM_Filter_AwdParamTypeDef::LowBreakSignal
uint32_t LowBreakSignal
Definition: stm32f4xx_hal_dfsdm.h:265
DFSDM_MultiChannelConfigTypeDef::DFSDM2ClockOut
uint32_t DFSDM2ClockOut
Definition: stm32f4xx_hal_dfsdm.h:306
DFSDM_MultiChannelConfigTypeDef::DFSDM1ClockIn
uint32_t DFSDM1ClockIn
Definition: stm32f4xx_hal_dfsdm.h:300
HAL_DFSDM_Channel_CallbackIDTypeDef
HAL_DFSDM_Channel_CallbackIDTypeDef
DFSDM channel callback ID enumeration definition.
Definition: stm32f4xx_hal_dfsdm.h:141
HAL_DFSDM_CHANNEL_SCD_CB_ID
@ HAL_DFSDM_CHANNEL_SCD_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:143
HAL_DFSDM_CHANNEL_CKAB_CB_ID
@ HAL_DFSDM_CHANNEL_CKAB_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:142
HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID
@ HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:145
HAL_DFSDM_CHANNEL_MSPINIT_CB_ID
@ HAL_DFSDM_CHANNEL_MSPINIT_CB_ID
Definition: stm32f4xx_hal_dfsdm.h:144
DFSDM_MultiChannelConfigTypeDef::DFSDM1DataDistribution
uint32_t DFSDM1DataDistribution
Definition: stm32f4xx_hal_dfsdm.h:318
DFSDM_Filter_HandleTypeDef
struct __DFSDM_Filter_HandleTypeDef else typedef struct endif DFSDM_Filter_HandleTypeDef
DFSDM filter handle structure definition.
DFSDM_MultiChannelConfigTypeDef::DFSDM1ClockOut
uint32_t DFSDM1ClockOut
Definition: stm32f4xx_hal_dfsdm.h:304
DFSDM_Filter_AwdParamTypeDef::Channel
uint32_t Channel
Definition: stm32f4xx_hal_dfsdm.h:257
DFSDM_MultiChannelConfigTypeDef::DFSDM2BitClkDistribution
uint32_t DFSDM2BitClkDistribution
Definition: stm32f4xx_hal_dfsdm.h:312
DFSDM_Filter_AwdParamTypeDef::DataSource
uint32_t DataSource
Definition: stm32f4xx_hal_dfsdm.h:255
DFSDM_Filter_AwdParamTypeDef
DFSDM filter analog watchdog parameters structure definition.
Definition: stm32f4xx_hal_dfsdm.h:254
DFSDM_MultiChannelConfigTypeDef
Synchronization parameters structure definition for STM32F413xx/STM32F423xx devices.
Definition: stm32f4xx_hal_dfsdm.h:299
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f4xx_hal_dma.h:139