STM32F4xx_HAL_Driver  1.8.3
stm32f4xx_ll_fsmc.h
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1 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32F4xx_LL_FSMC_H
21 #define STM32F4xx_LL_FSMC_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f4xx_hal_def.h"
29 
41 #if defined(FSMC_Bank1)
42 
43 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
44  ((__BANK__) == FSMC_NORSRAM_BANK2) || \
45  ((__BANK__) == FSMC_NORSRAM_BANK3) || \
46  ((__BANK__) == FSMC_NORSRAM_BANK4))
47 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
48  ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
49 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
50  ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
51  ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
52 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
53  ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
54  ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
55 #define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \
56  ((__SIZE__) == FSMC_PAGE_SIZE_128) || \
57  ((__SIZE__) == FSMC_PAGE_SIZE_256) || \
58  ((__SIZE__) == FSMC_PAGE_SIZE_512) || \
59  ((__SIZE__) == FSMC_PAGE_SIZE_1024))
60 #if defined(FSMC_BCR1_WFDIS)
61 #define IS_FSMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FSMC_WRITE_FIFO_DISABLE) || \
62  ((__FIFO__) == FSMC_WRITE_FIFO_ENABLE))
63 #endif /* FSMC_BCR1_WFDIS */
64 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
65  ((__MODE__) == FSMC_ACCESS_MODE_B) || \
66  ((__MODE__) == FSMC_ACCESS_MODE_C) || \
67  ((__MODE__) == FSMC_ACCESS_MODE_D))
68 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
69  ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
70 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
71  ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
72 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
73  ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
74 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
75  ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
76 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
77  ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
78 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
79  ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
80 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
81  ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
82 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
83  ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
84 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
85 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
86  ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
87 #define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
88  ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
89 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
90 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
91 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
92 #define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
93 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
94 #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
95 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
96 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
97 
98 #endif /* FSMC_Bank1 */
99 #if defined(FSMC_Bank2_3)
100 
101 #define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) || \
102  ((__BANK__) == FSMC_NAND_BANK3))
103 #define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
104  ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
105 #define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
106  ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
107 #define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
108  ((__STATE__) == FSMC_NAND_ECC_ENABLE))
109 
110 #define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
111  ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
112  ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
113  ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
114  ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
115  ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
116 #define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
117 #define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
118 #define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
119 #define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
120 #define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
121 #define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
122 #define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
123 
124 #endif /* FSMC_Bank2_3 */
125 #if defined(FSMC_Bank4)
126 #define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
127 
128 #endif /* FSMC_Bank4 */
129 
134 /* Exported typedef ----------------------------------------------------------*/
135 
140 #if defined(FSMC_Bank1)
141 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
142 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
143 #endif /* FSMC_Bank1 */
144 #if defined(FSMC_Bank2_3)
145 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
146 #endif /* FSMC_Bank2_3 */
147 #if defined(FSMC_Bank4)
148 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
149 #endif /* FSMC_Bank4 */
150 
151 #if defined(FSMC_Bank1)
152 #define FSMC_NORSRAM_DEVICE FSMC_Bank1
153 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
154 #endif /* FSMC_Bank1 */
155 #if defined(FSMC_Bank2_3)
156 #define FSMC_NAND_DEVICE FSMC_Bank2_3
157 #endif /* FSMC_Bank2_3 */
158 #if defined(FSMC_Bank4)
159 #define FSMC_PCCARD_DEVICE FSMC_Bank4
160 #endif /* FSMC_Bank4 */
161 
162 #if defined(FSMC_Bank1)
166 typedef struct
167 {
168  uint32_t NSBank;
171  uint32_t DataAddressMux;
175  uint32_t MemoryType;
179  uint32_t MemoryDataWidth;
182  uint32_t BurstAccessMode;
186  uint32_t WaitSignalPolarity;
190  uint32_t WrapMode;
195  uint32_t WaitSignalActive;
200  uint32_t WriteOperation;
203  uint32_t WaitSignal;
207  uint32_t ExtendedMode;
210  uint32_t AsynchronousWait;
214  uint32_t WriteBurst;
217  uint32_t ContinuousClock;
223  uint32_t WriteFifo;
229  uint32_t PageSize;
231 } FSMC_NORSRAM_InitTypeDef;
232 
236 typedef struct
237 {
238  uint32_t AddressSetupTime;
243  uint32_t AddressHoldTime;
248  uint32_t DataSetupTime;
254  uint32_t BusTurnAroundDuration;
259  uint32_t CLKDivision;
265  uint32_t DataLatency;
273  uint32_t AccessMode;
275 } FSMC_NORSRAM_TimingTypeDef;
276 #endif /* FSMC_Bank1 */
277 
278 #if defined(FSMC_Bank2_3)
282 typedef struct
283 {
284  uint32_t NandBank;
287  uint32_t Waitfeature;
290  uint32_t MemoryDataWidth;
293  uint32_t EccComputation;
296  uint32_t ECCPageSize;
299  uint32_t TCLRSetupTime;
303  uint32_t TARSetupTime;
306 } FSMC_NAND_InitTypeDef;
307 #endif /* FSMC_Bank2_3 */
308 
309 #if defined(FSMC_Bank2_3) || defined(FSMC_Bank4)
313 typedef struct
314 {
315  uint32_t SetupTime;
321  uint32_t WaitSetupTime;
327  uint32_t HoldSetupTime;
334  uint32_t HiZSetupTime;
339 } FSMC_NAND_PCC_TimingTypeDef;
340 #endif /* FSMC_Bank2_3 */
341 
342 #if defined(FSMC_Bank4)
346 typedef struct
347 {
348  uint32_t Waitfeature;
351  uint32_t TCLRSetupTime;
355  uint32_t TARSetupTime;
358 }FSMC_PCCARD_InitTypeDef;
359 #endif /* FSMC_Bank4 */
360 
365 /* Exported constants --------------------------------------------------------*/
369 #if defined(FSMC_Bank1)
370 
378 #define FSMC_NORSRAM_BANK1 (0x00000000U)
379 #define FSMC_NORSRAM_BANK2 (0x00000002U)
380 #define FSMC_NORSRAM_BANK3 (0x00000004U)
381 #define FSMC_NORSRAM_BANK4 (0x00000006U)
389 #define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
390 #define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
398 #define FSMC_MEMORY_TYPE_SRAM (0x00000000U)
399 #define FSMC_MEMORY_TYPE_PSRAM (0x00000004U)
400 #define FSMC_MEMORY_TYPE_NOR (0x00000008U)
408 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
409 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
410 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
418 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
419 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
427 #define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
428 #define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
436 #define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
437 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
446 #define FSMC_WRAP_MODE_DISABLE (0x00000000U)
447 #define FSMC_WRAP_MODE_ENABLE (0x00000400U)
455 #define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
456 #define FSMC_WAIT_TIMING_DURING_WS (0x00000800U)
464 #define FSMC_WRITE_OPERATION_DISABLE (0x00000000U)
465 #define FSMC_WRITE_OPERATION_ENABLE (0x00001000U)
473 #define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U)
474 #define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U)
482 #define FSMC_EXTENDED_MODE_DISABLE (0x00000000U)
483 #define FSMC_EXTENDED_MODE_ENABLE (0x00004000U)
491 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
492 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
500 #define FSMC_PAGE_SIZE_NONE (0x00000000U)
501 #define FSMC_PAGE_SIZE_128 FSMC_BCR1_CPSIZE_0
502 #define FSMC_PAGE_SIZE_256 FSMC_BCR1_CPSIZE_1
503 #define FSMC_PAGE_SIZE_512 (FSMC_BCR1_CPSIZE_0\
504  | FSMC_BCR1_CPSIZE_1)
505 #define FSMC_PAGE_SIZE_1024 FSMC_BCR1_CPSIZE_2
513 #define FSMC_WRITE_BURST_DISABLE (0x00000000U)
514 #define FSMC_WRITE_BURST_ENABLE (0x00080000U)
523 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
524 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
529 #if defined(FSMC_BCR1_WFDIS)
534 #define FSMC_WRITE_FIFO_DISABLE FSMC_BCR1_WFDIS
535 #define FSMC_WRITE_FIFO_ENABLE (0x00000000U)
536 #endif /* FSMC_BCR1_WFDIS */
544 #define FSMC_ACCESS_MODE_A (0x00000000U)
545 #define FSMC_ACCESS_MODE_B (0x10000000U)
546 #define FSMC_ACCESS_MODE_C (0x20000000U)
547 #define FSMC_ACCESS_MODE_D (0x30000000U)
555 #endif /* FSMC_Bank1 */
556 
557 #if defined(FSMC_Bank2_3) || defined(FSMC_Bank4)
558 
565 #if defined(FSMC_Bank2_3)
566 #define FSMC_NAND_BANK2 (0x00000010U)
567 #endif
568 #define FSMC_NAND_BANK3 (0x00000100U)
576 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U)
577 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U)
585 #if defined(FSMC_Bank4)
586 #define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U)
587 #endif /* FSMC_Bank4 */
588 #define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
596 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U)
597 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U)
605 #define FSMC_NAND_ECC_DISABLE (0x00000000U)
606 #define FSMC_NAND_ECC_ENABLE (0x00000040U)
614 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
615 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
616 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
617 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
618 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
619 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
627 #endif /* FSMC_Bank2_3 || FSMC_Bank4 */
628 
629 
633 #if defined(FSMC_Bank2_3) || defined(FSMC_Bank4)
634 #define FSMC_IT_RISING_EDGE (0x00000008U)
635 #define FSMC_IT_LEVEL (0x00000010U)
636 #define FSMC_IT_FALLING_EDGE (0x00000020U)
637 #endif /* FSMC_Bank2_3 || FSMC_Bank4 */
645 #if defined(FSMC_Bank2_3) || defined(FSMC_Bank4)
646 #define FSMC_FLAG_RISING_EDGE (0x00000001U)
647 #define FSMC_FLAG_LEVEL (0x00000002U)
648 #define FSMC_FLAG_FALLING_EDGE (0x00000004U)
649 #define FSMC_FLAG_FEMPT (0x00000040U)
650 #endif /* FSMC_Bank2_3 || FSMC_Bank4 */
658 #define FMC_WRITE_OPERATION_DISABLE FSMC_WRITE_OPERATION_DISABLE
659 #define FMC_WRITE_OPERATION_ENABLE FSMC_WRITE_OPERATION_ENABLE
660 
661 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8
662 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16
663 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32
664 
665 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
666 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
667 #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
668 #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
669 
670 #define FMC_NORSRAM_Init FSMC_NORSRAM_Init
671 #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
672 #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
673 #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
674 #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
675 #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
676 
677 #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
678 #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
679 
680 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
681 #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
682 #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
683 #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
684 
685 #define FMC_NAND_Init FSMC_NAND_Init
686 #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
687 #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
688 #define FMC_NAND_DeInit FSMC_NAND_DeInit
689 #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
690 #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
691 #define FMC_NAND_GetECC FSMC_NAND_GetECC
692 #define FMC_PCCARD_Init FSMC_PCCARD_Init
693 #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
694 #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
695 #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
696 #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
697 
698 #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
699 #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
700 #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
701 #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
702 #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
703 #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
704 #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
705 #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
706 #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
707 #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
708 #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
709 #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
710 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
711 
712 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
713 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
714 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
715 #define FMC_NAND_TypeDef FSMC_NAND_TypeDef
716 #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
717 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
718 
719 #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
720 #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
721 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
722 #define FMC_NAND_DEVICE FSMC_NAND_DEVICE
723 #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
724 
725 #define FMC_NAND_BANK2 FSMC_NAND_BANK2
726 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
727 
728 #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
729 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
730 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
731 
732 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
733 #define FMC_IT_LEVEL FSMC_IT_LEVEL
734 #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
735 #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
736 
737 #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
738 #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
739 #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
740 #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
753 /* Private macro -------------------------------------------------------------*/
757 #if defined(FSMC_Bank1)
769 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
770  |= FSMC_BCR1_MBKEN)
771 
778 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
779  &= ~FSMC_BCR1_MBKEN)
780 
784 #endif /* FSMC_Bank1 */
785 
786 #if defined(FSMC_Bank2_3)
798 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
799  ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
800 
807 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCR2_PBKEN): \
808  CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCR3_PBKEN))
809 
813 #endif /* FSMC_Bank2_3 */
814 
815 #if defined(FSMC_Bank4)
825 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
826 
832 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
837 #endif
838 #if defined(FSMC_Bank2_3)
855 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
856  ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
857 
869 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
870  ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
871 
884 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
885  (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
886 
899 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
900  ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
901 
905 #endif /* FSMC_Bank2_3 */
906 
907 #if defined(FSMC_Bank4)
923 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
924 
935 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
936 
948 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
949 
961 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
962 
966 #endif
967 
976 /* Private functions ---------------------------------------------------------*/
981 #if defined(FSMC_Bank1)
988 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
989  FSMC_NORSRAM_InitTypeDef *Init);
990 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
991  FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
992 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
993  FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
994  uint32_t ExtendedMode);
995 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
996  FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1004 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1005 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1012 #endif /* FSMC_Bank1 */
1013 
1014 #if defined(FSMC_Bank2_3)
1021 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
1022 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
1023  FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1024 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
1025  FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1026 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
1034 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
1035 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
1036 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
1037  uint32_t Timeout);
1044 #endif /* FSMC_Bank2_3 */
1045 
1046 #if defined(FSMC_Bank4)
1053 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
1054 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
1055  FSMC_NAND_PCC_TimingTypeDef *Timing);
1056 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
1057  FSMC_NAND_PCC_TimingTypeDef *Timing);
1058 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
1059  FSMC_NAND_PCC_TimingTypeDef *Timing);
1060 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
1067 #endif /* FSMC_Bank4 */
1068 
1069 
1082 #ifdef __cplusplus
1083 }
1084 #endif
1085 
1086 #endif /* STM32F4xx_LL_FSMC_H */
FSMC_NORSRAM_InitTypeDef::WaitSignal
uint32_t WaitSignal
Definition: stm32f4xx_ll_fsmc.h:203
FSMC_NAND_PCC_TimingTypeDef::HoldSetupTime
uint32_t HoldSetupTime
Definition: stm32f4xx_ll_fsmc.h:327
FSMC_NAND_InitTypeDef::EccComputation
uint32_t EccComputation
Definition: stm32f4xx_ll_fsmc.h:293
FSMC_NORSRAM_TimingTypeDef::CLKDivision
uint32_t CLKDivision
Definition: stm32f4xx_ll_fsmc.h:259
FSMC_NORSRAM_InitTypeDef::ContinuousClock
uint32_t ContinuousClock
Definition: stm32f4xx_ll_fsmc.h:217
FSMC_NORSRAM_InitTypeDef::DataAddressMux
uint32_t DataAddressMux
Definition: stm32f4xx_ll_fsmc.h:171
FSMC_NORSRAM_InitTypeDef::WriteOperation
uint32_t WriteOperation
Definition: stm32f4xx_ll_fsmc.h:200
FSMC_NORSRAM_InitTypeDef::WrapMode
uint32_t WrapMode
Definition: stm32f4xx_ll_fsmc.h:190
FSMC_NORSRAM_InitTypeDef::AsynchronousWait
uint32_t AsynchronousWait
Definition: stm32f4xx_ll_fsmc.h:210
FSMC_NAND_InitTypeDef::ECCPageSize
uint32_t ECCPageSize
Definition: stm32f4xx_ll_fsmc.h:296
FSMC_NORSRAM_TimingTypeDef::DataLatency
uint32_t DataLatency
Definition: stm32f4xx_ll_fsmc.h:265
FSMC_NAND_InitTypeDef::Waitfeature
uint32_t Waitfeature
Definition: stm32f4xx_ll_fsmc.h:287
FSMC_NAND_InitTypeDef::TCLRSetupTime
uint32_t TCLRSetupTime
Definition: stm32f4xx_ll_fsmc.h:299
FSMC_NORSRAM_InitTypeDef::WriteBurst
uint32_t WriteBurst
Definition: stm32f4xx_ll_fsmc.h:214
FSMC_NORSRAM_InitTypeDef::NSBank
uint32_t NSBank
Definition: stm32f4xx_ll_fsmc.h:168
FSMC_NORSRAM_InitTypeDef::MemoryType
uint32_t MemoryType
Definition: stm32f4xx_ll_fsmc.h:175
FSMC_NORSRAM_InitTypeDef::PageSize
uint32_t PageSize
Definition: stm32f4xx_ll_fsmc.h:229
FSMC_PCCARD_InitTypeDef::Waitfeature
uint32_t Waitfeature
Definition: stm32f4xx_ll_fsmc.h:348
FSMC_PCCARD_InitTypeDef::TARSetupTime
uint32_t TARSetupTime
Definition: stm32f4xx_ll_fsmc.h:355
FSMC_NAND_PCC_TimingTypeDef::WaitSetupTime
uint32_t WaitSetupTime
Definition: stm32f4xx_ll_fsmc.h:321
FSMC_NAND_InitTypeDef::MemoryDataWidth
uint32_t MemoryDataWidth
Definition: stm32f4xx_ll_fsmc.h:290
FSMC_NAND_PCC_TimingTypeDef::SetupTime
uint32_t SetupTime
Definition: stm32f4xx_ll_fsmc.h:315
FSMC_NAND_PCC_TimingTypeDef::HiZSetupTime
uint32_t HiZSetupTime
Definition: stm32f4xx_ll_fsmc.h:334
FSMC_NORSRAM_TimingTypeDef::AddressHoldTime
uint32_t AddressHoldTime
Definition: stm32f4xx_ll_fsmc.h:243
FSMC_NORSRAM_InitTypeDef::BurstAccessMode
uint32_t BurstAccessMode
Definition: stm32f4xx_ll_fsmc.h:182
FSMC_NAND_InitTypeDef::NandBank
uint32_t NandBank
Definition: stm32f4xx_ll_fsmc.h:284
FSMC_NORSRAM_InitTypeDef::ExtendedMode
uint32_t ExtendedMode
Definition: stm32f4xx_ll_fsmc.h:207
FSMC_PCCARD_InitTypeDef::TCLRSetupTime
uint32_t TCLRSetupTime
Definition: stm32f4xx_ll_fsmc.h:351
FSMC_NORSRAM_InitTypeDef::WriteFifo
uint32_t WriteFifo
Definition: stm32f4xx_ll_fsmc.h:223
FSMC_NORSRAM_TimingTypeDef::AccessMode
uint32_t AccessMode
Definition: stm32f4xx_ll_fsmc.h:273
FSMC_NORSRAM_TimingTypeDef::DataSetupTime
uint32_t DataSetupTime
Definition: stm32f4xx_ll_fsmc.h:248
FSMC_NORSRAM_InitTypeDef::MemoryDataWidth
uint32_t MemoryDataWidth
Definition: stm32f4xx_ll_fsmc.h:179
FSMC_NORSRAM_InitTypeDef::WaitSignalPolarity
uint32_t WaitSignalPolarity
Definition: stm32f4xx_ll_fsmc.h:186
FSMC_NORSRAM_TimingTypeDef::AddressSetupTime
uint32_t AddressSetupTime
Definition: stm32f4xx_ll_fsmc.h:238
FSMC_NAND_InitTypeDef::TARSetupTime
uint32_t TARSetupTime
Definition: stm32f4xx_ll_fsmc.h:303
FSMC_NORSRAM_TimingTypeDef::BusTurnAroundDuration
uint32_t BusTurnAroundDuration
Definition: stm32f4xx_ll_fsmc.h:254
FSMC_NORSRAM_InitTypeDef::WaitSignalActive
uint32_t WaitSignalActive
Definition: stm32f4xx_ll_fsmc.h:195
FSMC_NAND_InitTypeDef
FSMC NAND Configuration Structure definition.
Definition: stm32f4xx_ll_fsmc.h:283
FSMC_NAND_PCC_TimingTypeDef
FSMC NAND Timing parameters structure definition.
Definition: stm32f4xx_ll_fsmc.h:314
FSMC_NORSRAM_InitTypeDef
FSMC NORSRAM Configuration Structure definition.
Definition: stm32f4xx_ll_fsmc.h:167
FSMC_NORSRAM_TimingTypeDef
FSMC NORSRAM Timing parameters structure definition.
Definition: stm32f4xx_ll_fsmc.h:237
FSMC_PCCARD_InitTypeDef
FSMC PCCARD Configuration Structure definition.
Definition: stm32f4xx_ll_fsmc.h:347
FSMC_NAND_AttributeSpace_Timing_Init
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
Initializes the FSMC_NAND Attribute space Timing according to the specified parameters in the FSMC_NA...
Definition: stm32f4xx_ll_fsmc.c:666
FSMC_NAND_DeInit
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
DeInitializes the FSMC_NAND device.
Definition: stm32f4xx_ll_fsmc.c:704
FSMC_NAND_Init
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
Initializes the FSMC_NAND device according to the specified control parameters in the FSMC_NAND_Handl...
Definition: stm32f4xx_ll_fsmc.c:579
FSMC_NAND_CommonSpace_Timing_Init
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
Initializes the FSMC_NAND Common space Timing according to the specified parameters in the FSMC_NAND_...
Definition: stm32f4xx_ll_fsmc.c:626
FSMC_NAND_ECC_Enable
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
Enables dynamically FSMC_NAND ECC feature.
Definition: stm32f4xx_ll_fsmc.c:761
FSMC_NAND_ECC_Disable
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
Disables dynamically FSMC_NAND ECC feature.
Definition: stm32f4xx_ll_fsmc.c:787
FSMC_NAND_GetECC
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
Disables dynamically FSMC_NAND ECC feature.
Definition: stm32f4xx_ll_fsmc.c:814
FSMC_NORSRAM_Init
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init)
Initialize the FSMC_NORSRAM device according to the specified control parameters in the FSMC_NORSRAM_...
Definition: stm32f4xx_ll_fsmc.c:220
FSMC_NORSRAM_Extended_Timing_Init
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
Initialize the FSMC_NORSRAM Extended mode Timing according to the specified parameters in the FSMC_NO...
Definition: stm32f4xx_ll_fsmc.c:431
FSMC_NORSRAM_DeInit
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
DeInitialize the FSMC_NORSRAM peripheral.
Definition: stm32f4xx_ll_fsmc.c:342
FSMC_NORSRAM_Timing_Init
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
Initialize the FSMC_NORSRAM Timing according to the specified parameters in the FSMC_NORSRAM_TimingTy...
Definition: stm32f4xx_ll_fsmc.c:379
FSMC_NORSRAM_WriteOperation_Enable
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
Enables dynamically FSMC_NORSRAM write operation.
Definition: stm32f4xx_ll_fsmc.c:489
FSMC_NORSRAM_WriteOperation_Disable
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
Disables dynamically FSMC_NORSRAM write operation.
Definition: stm32f4xx_ll_fsmc.c:507
FSMC_PCCARD_DeInit
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
DeInitializes the FSMC_PCCARD device.
Definition: stm32f4xx_ll_fsmc.c:1025
FSMC_PCCARD_Init
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
Initializes the FSMC_PCCARD device according to the specified control parameters in the FSMC_PCCARD_H...
Definition: stm32f4xx_ll_fsmc.c:907
FSMC_PCCARD_IOSpace_Timing_Init
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
Initializes the FSMC_PCCARD IO space Timing according to the specified parameters in the FSMC_NAND_PC...
Definition: stm32f4xx_ll_fsmc.c:998
FSMC_PCCARD_AttributeSpace_Timing_Init
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
Initializes the FSMC_PCCARD Attribute space Timing according to the specified parameters in the FSMC_...
Definition: stm32f4xx_ll_fsmc.c:969
FSMC_PCCARD_CommonSpace_Timing_Init
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
Initializes the FSMC_PCCARD Common space Timing according to the specified parameters in the FSMC_NAN...
Definition: stm32f4xx_ll_fsmc.c:940
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.