STM32F4xx_HAL_Driver  1.8.3
stm32f4xx_ll_fmc.h
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1 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32F4xx_LL_FMC_H
21 #define STM32F4xx_LL_FMC_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32f4xx_hal_def.h"
29 
41 #if defined(FMC_Bank1)
42 
43 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
44  ((__BANK__) == FMC_NORSRAM_BANK2) || \
45  ((__BANK__) == FMC_NORSRAM_BANK3) || \
46  ((__BANK__) == FMC_NORSRAM_BANK4))
47 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
48  ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
49 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
50  ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
51  ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
52 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
53  ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
54  ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
55 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
56  ((__SIZE__) == FMC_PAGE_SIZE_128) || \
57  ((__SIZE__) == FMC_PAGE_SIZE_256) || \
58  ((__SIZE__) == FMC_PAGE_SIZE_512) || \
59  ((__SIZE__) == FMC_PAGE_SIZE_1024))
60 #if defined(FMC_BCR1_WFDIS)
61 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
62  ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
63 #endif /* FMC_BCR1_WFDIS */
64 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
65  ((__MODE__) == FMC_ACCESS_MODE_B) || \
66  ((__MODE__) == FMC_ACCESS_MODE_C) || \
67  ((__MODE__) == FMC_ACCESS_MODE_D))
68 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
69  ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
70 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
71  ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
72 #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
73  ((__MODE__) == FMC_WRAP_MODE_ENABLE))
74 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
75  ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
76 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
77  ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
78 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
79  ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
80 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
81  ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
82 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
83  ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
84 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
85 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
86  ((__BURST__) == FMC_WRITE_BURST_ENABLE))
87 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
88  ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
89 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
90 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
91 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
92 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
93 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
94 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
95 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
96 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
97 
98 #endif /* FMC_Bank1 */
99 #if (defined(FMC_Bank3) || defined(FMC_Bank2_3))
100 
101 #if defined(FMC_Bank2_3)
102 #define IS_FMC_NAND_BANK(__BANK__) (((__BANK__) == FMC_NAND_BANK2) || \
103  ((__BANK__) == FMC_NAND_BANK3))
104 #else
105 #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
106 #endif /* FMC_Bank2_3 */
107 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
108  ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
109 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
110  ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
111 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
112  ((__STATE__) == FMC_NAND_ECC_ENABLE))
113 
114 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
115  ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
116  ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
117  ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
118  ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
119  ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
120 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
121 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
122 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
123 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
124 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
125 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
126 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
127 
128 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
129 #if defined(FMC_Bank4)
130 #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
131 
132 #endif /* FMC_Bank4 */
133 #if defined(FMC_Bank5_6)
134 
135 #define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
136  ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
137  ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32))
138 #define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
139  ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
140 #define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \
141  ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \
142  ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
143 #define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \
144  ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
145 #define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \
146  ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \
147  ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
148 #define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \
149  ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \
150  ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \
151  ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
152  ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \
153  ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
154  ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
155 #define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \
156  ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \
157  ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
158 #define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
159 #define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
160 #define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))
161 #define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
162 #define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))
163 #define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
164 #define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
165 #define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U))
166 #define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U)
167 #define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U)
168 #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
169 #define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \
170  ((__BANK__) == FMC_SDRAM_BANK2))
171 #define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
172  ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
173  ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
174  ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11))
175 #define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \
176  ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \
177  ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13))
178 #define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
179  ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4))
180 #define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \
181  ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \
182  ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3))
183 
184 #endif /* FMC_Bank5_6 */
185 
190 /* Exported typedef ----------------------------------------------------------*/
191 
196 #if defined(FMC_Bank1)
197 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
198 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
199 #endif /* FMC_Bank1 */
200 #if defined(FMC_Bank2_3)
201 #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
202 #else
203 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
204 #endif /* FMC_Bank2_3 */
205 #if defined(FMC_Bank4)
206 #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
207 #endif /* FMC_Bank4 */
208 #if defined(FMC_Bank5_6)
209 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
210 #endif /* FMC_Bank5_6 */
211 
212 #if defined(FMC_Bank1)
213 #define FMC_NORSRAM_DEVICE FMC_Bank1
214 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
215 #endif /* FMC_Bank1 */
216 #if defined(FMC_Bank2_3)
217 #define FMC_NAND_DEVICE FMC_Bank2_3
218 #else
219 #define FMC_NAND_DEVICE FMC_Bank3
220 #endif /* FMC_Bank2_3 */
221 #if defined(FMC_Bank4)
222 #define FMC_PCCARD_DEVICE FMC_Bank4
223 #endif /* FMC_Bank4 */
224 #if defined(FMC_Bank5_6)
225 #define FMC_SDRAM_DEVICE FMC_Bank5_6
226 #endif /* FMC_Bank5_6 */
227 
228 #if defined(FMC_Bank1)
232 typedef struct
233 {
234  uint32_t NSBank;
237  uint32_t DataAddressMux;
241  uint32_t MemoryType;
245  uint32_t MemoryDataWidth;
248  uint32_t BurstAccessMode;
252  uint32_t WaitSignalPolarity;
256  uint32_t WrapMode;
261  uint32_t WaitSignalActive;
266  uint32_t WriteOperation;
269  uint32_t WaitSignal;
273  uint32_t ExtendedMode;
276  uint32_t AsynchronousWait;
280  uint32_t WriteBurst;
283  uint32_t ContinuousClock;
288  uint32_t WriteFifo;
294  uint32_t PageSize;
296 } FMC_NORSRAM_InitTypeDef;
297 
301 typedef struct
302 {
303  uint32_t AddressSetupTime;
308  uint32_t AddressHoldTime;
313  uint32_t DataSetupTime;
319  uint32_t BusTurnAroundDuration;
324  uint32_t CLKDivision;
330  uint32_t DataLatency;
338  uint32_t AccessMode;
340 } FMC_NORSRAM_TimingTypeDef;
341 #endif /* FMC_Bank1 */
342 
343 #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
347 typedef struct
348 {
349  uint32_t NandBank;
352  uint32_t Waitfeature;
355  uint32_t MemoryDataWidth;
358  uint32_t EccComputation;
361  uint32_t ECCPageSize;
364  uint32_t TCLRSetupTime;
368  uint32_t TARSetupTime;
371 } FMC_NAND_InitTypeDef;
372 #endif /* FMC_Bank3 || FMC_Bank2_3 */
373 
374 #if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4)
378 typedef struct
379 {
380  uint32_t SetupTime;
386  uint32_t WaitSetupTime;
392  uint32_t HoldSetupTime;
399  uint32_t HiZSetupTime;
404 } FMC_NAND_PCC_TimingTypeDef;
405 #endif /* FMC_Bank3 || FMC_Bank2_3 */
406 
407 #if defined(FMC_Bank4)
411 typedef struct
412 {
413  uint32_t Waitfeature;
416  uint32_t TCLRSetupTime;
420  uint32_t TARSetupTime;
423 }FMC_PCCARD_InitTypeDef;
424 #endif /* FMC_Bank4 */
425 
426 #if defined(FMC_Bank5_6)
430 typedef struct
431 {
432  uint32_t SDBank;
435  uint32_t ColumnBitsNumber;
438  uint32_t RowBitsNumber;
441  uint32_t MemoryDataWidth;
444  uint32_t InternalBankNumber;
447  uint32_t CASLatency;
450  uint32_t WriteProtection;
453  uint32_t SDClockPeriod;
457  uint32_t ReadBurst;
461  uint32_t ReadPipeDelay;
463 } FMC_SDRAM_InitTypeDef;
464 
468 typedef struct
469 {
470  uint32_t LoadToActiveDelay;
474  uint32_t ExitSelfRefreshDelay;
478  uint32_t SelfRefreshTime;
482  uint32_t RowCycleDelay;
487  uint32_t WriteRecoveryTime;
490  uint32_t RPDelay;
494  uint32_t RCDDelay;
497 } FMC_SDRAM_TimingTypeDef;
498 
502 typedef struct
503 {
504  uint32_t CommandMode;
507  uint32_t CommandTarget;
510  uint32_t AutoRefreshNumber;
514  uint32_t ModeRegisterDefinition;
515 } FMC_SDRAM_CommandTypeDef;
516 #endif /* FMC_Bank5_6 */
521 /* Exported constants --------------------------------------------------------*/
525 #if defined(FMC_Bank1)
526 
534 #define FMC_NORSRAM_BANK1 (0x00000000U)
535 #define FMC_NORSRAM_BANK2 (0x00000002U)
536 #define FMC_NORSRAM_BANK3 (0x00000004U)
537 #define FMC_NORSRAM_BANK4 (0x00000006U)
545 #define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
546 #define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
554 #define FMC_MEMORY_TYPE_SRAM (0x00000000U)
555 #define FMC_MEMORY_TYPE_PSRAM (0x00000004U)
556 #define FMC_MEMORY_TYPE_NOR (0x00000008U)
564 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
565 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
566 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
574 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
575 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
583 #define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
584 #define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
592 #define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
593 #define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
602 #define FMC_WRAP_MODE_DISABLE (0x00000000U)
603 #define FMC_WRAP_MODE_ENABLE (0x00000400U)
611 #define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
612 #define FMC_WAIT_TIMING_DURING_WS (0x00000800U)
620 #define FMC_WRITE_OPERATION_DISABLE (0x00000000U)
621 #define FMC_WRITE_OPERATION_ENABLE (0x00001000U)
629 #define FMC_WAIT_SIGNAL_DISABLE (0x00000000U)
630 #define FMC_WAIT_SIGNAL_ENABLE (0x00002000U)
638 #define FMC_EXTENDED_MODE_DISABLE (0x00000000U)
639 #define FMC_EXTENDED_MODE_ENABLE (0x00004000U)
647 #define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
648 #define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
656 #define FMC_PAGE_SIZE_NONE (0x00000000U)
657 #define FMC_PAGE_SIZE_128 FMC_BCR1_CPSIZE_0
658 #define FMC_PAGE_SIZE_256 FMC_BCR1_CPSIZE_1
659 #define FMC_PAGE_SIZE_512 (FMC_BCR1_CPSIZE_0\
660  | FMC_BCR1_CPSIZE_1)
661 #define FMC_PAGE_SIZE_1024 FMC_BCR1_CPSIZE_2
669 #define FMC_WRITE_BURST_DISABLE (0x00000000U)
670 #define FMC_WRITE_BURST_ENABLE (0x00080000U)
678 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
679 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
684 #if defined(FMC_BCR1_WFDIS)
689 #define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS
690 #define FMC_WRITE_FIFO_ENABLE (0x00000000U)
691 #endif /* FMC_BCR1_WFDIS */
699 #define FMC_ACCESS_MODE_A (0x00000000U)
700 #define FMC_ACCESS_MODE_B (0x10000000U)
701 #define FMC_ACCESS_MODE_C (0x20000000U)
702 #define FMC_ACCESS_MODE_D (0x30000000U)
710 #endif /* FMC_Bank1 */
711 
712 #if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4)
713 
720 #if defined(FMC_Bank2_3)
721 #define FMC_NAND_BANK2 (0x00000010U)
722 #endif
723 #define FMC_NAND_BANK3 (0x00000100U)
731 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U)
732 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U)
740 #if defined(FMC_Bank4)
741 #define FMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U)
742 #endif /* FMC_Bank4 */
743 #define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
751 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U)
752 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U)
760 #define FMC_NAND_ECC_DISABLE (0x00000000U)
761 #define FMC_NAND_ECC_ENABLE (0x00000040U)
769 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
770 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
771 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
772 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
773 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
774 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
782 #endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */
783 
784 #if defined(FMC_Bank5_6)
791 #define FMC_SDRAM_BANK1 (0x00000000U)
792 #define FMC_SDRAM_BANK2 (0x00000001U)
800 #define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U)
801 #define FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U)
802 #define FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U)
803 #define FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U)
811 #define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U)
812 #define FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U)
813 #define FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U)
821 #define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U)
822 #define FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U)
823 #define FMC_SDRAM_MEM_BUS_WIDTH_32 (0x00000020U)
831 #define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U)
832 #define FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U)
840 #define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U)
841 #define FMC_SDRAM_CAS_LATENCY_2 (0x00000100U)
842 #define FMC_SDRAM_CAS_LATENCY_3 (0x00000180U)
850 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U)
851 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U)
859 #define FMC_SDRAM_CLOCK_DISABLE (0x00000000U)
860 #define FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U)
861 #define FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U)
869 #define FMC_SDRAM_RBURST_DISABLE (0x00000000U)
870 #define FMC_SDRAM_RBURST_ENABLE (0x00001000U)
878 #define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U)
879 #define FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U)
880 #define FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U)
888 #define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U)
889 #define FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U)
890 #define FMC_SDRAM_CMD_PALL (0x00000002U)
891 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U)
892 #define FMC_SDRAM_CMD_LOAD_MODE (0x00000004U)
893 #define FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U)
894 #define FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U)
902 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
903 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
904 #define FMC_SDRAM_CMD_TARGET_BANK1_2 (0x00000018U)
912 #define FMC_SDRAM_NORMAL_MODE (0x00000000U)
913 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
914 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
923 #endif /* FMC_Bank5_6 */
924 
928 #if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4)
929 #define FMC_IT_RISING_EDGE (0x00000008U)
930 #define FMC_IT_LEVEL (0x00000010U)
931 #define FMC_IT_FALLING_EDGE (0x00000020U)
932 #endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */
933 #if defined(FMC_Bank5_6)
934 #define FMC_IT_REFRESH_ERROR (0x00004000U)
935 #endif /* FMC_Bank5_6 */
943 #if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4)
944 #define FMC_FLAG_RISING_EDGE (0x00000001U)
945 #define FMC_FLAG_LEVEL (0x00000002U)
946 #define FMC_FLAG_FALLING_EDGE (0x00000004U)
947 #define FMC_FLAG_FEMPT (0x00000040U)
948 #endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */
949 #if defined(FMC_Bank5_6)
950 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
951 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
952 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
953 #endif /* FMC_Bank5_6 */
966 /* Private macro -------------------------------------------------------------*/
970 #if defined(FMC_Bank1)
982 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
983  |= FMC_BCR1_MBKEN)
984 
991 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
992  &= ~FMC_BCR1_MBKEN)
993 
997 #endif /* FMC_Bank1 */
998 
999 #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
1011 #if defined(FMC_Bank2_3)
1012 #if defined (FMC_PCR_PBKEN)
1013 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
1014 #else
1015 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
1016  ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
1017 #endif /* FMC_PCR_PBKEN */
1018 #else
1019 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
1020 #endif /* FMC_Bank2_3 */
1021 
1028 #if defined(FMC_Bank2_3)
1029 #if defined (FMC_PCR_PBKEN)
1030 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
1031 #else
1032 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCR2_PBKEN): \
1033  CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCR3_PBKEN))
1034 #endif /* FMC_PCR_PBKEN */
1035 #else
1036 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
1037 #endif /* FMC_Bank2_3 */
1038 
1042 #endif /* FMC_Bank3 || FMC_Bank2_3 */
1043 
1044 #if defined(FMC_Bank4)
1054 #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
1055 
1061 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
1066 #endif
1067 #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
1084 #if defined(FMC_Bank2_3)
1085 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
1086  ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
1087 #else
1088 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
1089 #endif /* FMC_Bank2_3 */
1090 
1102 #if defined(FMC_Bank2_3)
1103 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
1104  ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
1105 #else
1106 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
1107 #endif /* FMC_Bank2_3 */
1108 
1121 #if defined(FMC_Bank2_3)
1122 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
1123  (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
1124 #else
1125 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
1126 #endif /* FMC_Bank2_3 */
1127 
1140 #if defined(FMC_Bank2_3)
1141 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
1142  ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
1143 #else
1144 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
1145 #endif /* FMC_Bank2_3 */
1146 
1150 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
1151 
1152 #if defined(FMC_Bank4)
1168 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
1169 
1180 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
1181 
1193 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
1194 
1206 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
1207 
1211 #endif
1212 
1213 #if defined(FMC_Bank5_6)
1227 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
1228 
1237 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
1238 
1249 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
1250 
1259 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
1260 
1264 #endif /* FMC_Bank5_6 */
1273 /* Private functions ---------------------------------------------------------*/
1278 #if defined(FMC_Bank1)
1285 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
1286  FMC_NORSRAM_InitTypeDef *Init);
1287 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
1288  FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1289 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
1290  FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
1291  uint32_t ExtendedMode);
1292 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
1293  FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1301 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1302 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1309 #endif /* FMC_Bank1 */
1310 
1311 #if defined(FMC_Bank3) || defined(FMC_Bank2_3)
1318 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
1319 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
1320  FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1321 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
1322  FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1323 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1331 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1332 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1333 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
1334  uint32_t Timeout);
1341 #endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
1342 
1343 #if defined(FMC_Bank4)
1350 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
1351 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
1352  FMC_NAND_PCC_TimingTypeDef *Timing);
1353 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
1354  FMC_NAND_PCC_TimingTypeDef *Timing);
1355 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
1356  FMC_NAND_PCC_TimingTypeDef *Timing);
1357 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
1364 #endif /* FMC_Bank4 */
1365 
1366 #if defined(FMC_Bank5_6)
1373 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
1374 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
1375  FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
1376 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1384 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1385 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1386 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
1387  FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
1388 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
1389 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
1390  uint32_t AutoRefreshNumber);
1391 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1398 #endif /* FMC_Bank5_6 */
1399 
1412 #ifdef __cplusplus
1413 }
1414 #endif
1415 
1416 #endif /* STM32F4xx_LL_FMC_H */
FMC_SDRAM_TimingTypeDef::ExitSelfRefreshDelay
uint32_t ExitSelfRefreshDelay
Definition: stm32f4xx_ll_fmc.h:474
FMC_NORSRAM_TimingTypeDef::CLKDivision
uint32_t CLKDivision
Definition: stm32f4xx_ll_fmc.h:324
FMC_NAND_PCC_TimingTypeDef::HiZSetupTime
uint32_t HiZSetupTime
Definition: stm32f4xx_ll_fmc.h:399
FMC_SDRAM_InitTypeDef::InternalBankNumber
uint32_t InternalBankNumber
Definition: stm32f4xx_ll_fmc.h:444
FMC_PCCARD_InitTypeDef::TARSetupTime
uint32_t TARSetupTime
Definition: stm32f4xx_ll_fmc.h:420
FMC_SDRAM_CommandTypeDef::CommandTarget
uint32_t CommandTarget
Definition: stm32f4xx_ll_fmc.h:507
FMC_NORSRAM_InitTypeDef::WrapMode
uint32_t WrapMode
Definition: stm32f4xx_ll_fmc.h:256
FMC_SDRAM_CommandTypeDef::AutoRefreshNumber
uint32_t AutoRefreshNumber
Definition: stm32f4xx_ll_fmc.h:510
FMC_NORSRAM_InitTypeDef::MemoryDataWidth
uint32_t MemoryDataWidth
Definition: stm32f4xx_ll_fmc.h:245
FMC_SDRAM_InitTypeDef::ColumnBitsNumber
uint32_t ColumnBitsNumber
Definition: stm32f4xx_ll_fmc.h:435
FMC_SDRAM_InitTypeDef::ReadPipeDelay
uint32_t ReadPipeDelay
Definition: stm32f4xx_ll_fmc.h:461
FMC_SDRAM_InitTypeDef::MemoryDataWidth
uint32_t MemoryDataWidth
Definition: stm32f4xx_ll_fmc.h:441
FMC_NORSRAM_InitTypeDef::WriteBurst
uint32_t WriteBurst
Definition: stm32f4xx_ll_fmc.h:280
FMC_NORSRAM_TimingTypeDef::AddressSetupTime
uint32_t AddressSetupTime
Definition: stm32f4xx_ll_fmc.h:303
FMC_NORSRAM_InitTypeDef::PageSize
uint32_t PageSize
Definition: stm32f4xx_ll_fmc.h:294
FMC_NORSRAM_TimingTypeDef::BusTurnAroundDuration
uint32_t BusTurnAroundDuration
Definition: stm32f4xx_ll_fmc.h:319
FMC_SDRAM_TimingTypeDef::RPDelay
uint32_t RPDelay
Definition: stm32f4xx_ll_fmc.h:490
FMC_NORSRAM_InitTypeDef::BurstAccessMode
uint32_t BurstAccessMode
Definition: stm32f4xx_ll_fmc.h:248
FMC_NORSRAM_InitTypeDef::ExtendedMode
uint32_t ExtendedMode
Definition: stm32f4xx_ll_fmc.h:273
FMC_NORSRAM_InitTypeDef::MemoryType
uint32_t MemoryType
Definition: stm32f4xx_ll_fmc.h:241
FMC_NAND_PCC_TimingTypeDef::HoldSetupTime
uint32_t HoldSetupTime
Definition: stm32f4xx_ll_fmc.h:392
FMC_NORSRAM_InitTypeDef::DataAddressMux
uint32_t DataAddressMux
Definition: stm32f4xx_ll_fmc.h:237
FMC_SDRAM_InitTypeDef::WriteProtection
uint32_t WriteProtection
Definition: stm32f4xx_ll_fmc.h:450
FMC_PCCARD_InitTypeDef::TCLRSetupTime
uint32_t TCLRSetupTime
Definition: stm32f4xx_ll_fmc.h:416
FMC_NORSRAM_InitTypeDef::WriteFifo
uint32_t WriteFifo
Definition: stm32f4xx_ll_fmc.h:288
FMC_NORSRAM_TimingTypeDef::DataSetupTime
uint32_t DataSetupTime
Definition: stm32f4xx_ll_fmc.h:313
FMC_NORSRAM_InitTypeDef::AsynchronousWait
uint32_t AsynchronousWait
Definition: stm32f4xx_ll_fmc.h:276
FMC_NORSRAM_InitTypeDef::WriteOperation
uint32_t WriteOperation
Definition: stm32f4xx_ll_fmc.h:266
FMC_NORSRAM_TimingTypeDef::AccessMode
uint32_t AccessMode
Definition: stm32f4xx_ll_fmc.h:338
FMC_NORSRAM_InitTypeDef::WaitSignalActive
uint32_t WaitSignalActive
Definition: stm32f4xx_ll_fmc.h:261
FMC_NORSRAM_InitTypeDef::WaitSignal
uint32_t WaitSignal
Definition: stm32f4xx_ll_fmc.h:269
FMC_NAND_PCC_TimingTypeDef::SetupTime
uint32_t SetupTime
Definition: stm32f4xx_ll_fmc.h:380
FMC_PCCARD_InitTypeDef::Waitfeature
uint32_t Waitfeature
Definition: stm32f4xx_ll_fmc.h:413
FMC_SDRAM_TimingTypeDef::SelfRefreshTime
uint32_t SelfRefreshTime
Definition: stm32f4xx_ll_fmc.h:478
FMC_SDRAM_InitTypeDef::RowBitsNumber
uint32_t RowBitsNumber
Definition: stm32f4xx_ll_fmc.h:438
FMC_NAND_InitTypeDef::TCLRSetupTime
uint32_t TCLRSetupTime
Definition: stm32f4xx_ll_fmc.h:364
FMC_NORSRAM_TimingTypeDef::AddressHoldTime
uint32_t AddressHoldTime
Definition: stm32f4xx_ll_fmc.h:308
FMC_SDRAM_TimingTypeDef::RCDDelay
uint32_t RCDDelay
Definition: stm32f4xx_ll_fmc.h:494
FMC_SDRAM_TimingTypeDef::WriteRecoveryTime
uint32_t WriteRecoveryTime
Definition: stm32f4xx_ll_fmc.h:487
FMC_NAND_InitTypeDef::TARSetupTime
uint32_t TARSetupTime
Definition: stm32f4xx_ll_fmc.h:368
FMC_SDRAM_TimingTypeDef::LoadToActiveDelay
uint32_t LoadToActiveDelay
Definition: stm32f4xx_ll_fmc.h:470
FMC_SDRAM_InitTypeDef::CASLatency
uint32_t CASLatency
Definition: stm32f4xx_ll_fmc.h:447
FMC_SDRAM_CommandTypeDef::ModeRegisterDefinition
uint32_t ModeRegisterDefinition
Definition: stm32f4xx_ll_fmc.h:514
FMC_SDRAM_InitTypeDef::ReadBurst
uint32_t ReadBurst
Definition: stm32f4xx_ll_fmc.h:457
FMC_NAND_PCC_TimingTypeDef::WaitSetupTime
uint32_t WaitSetupTime
Definition: stm32f4xx_ll_fmc.h:386
FMC_NORSRAM_InitTypeDef::WaitSignalPolarity
uint32_t WaitSignalPolarity
Definition: stm32f4xx_ll_fmc.h:252
FMC_SDRAM_CommandTypeDef::CommandMode
uint32_t CommandMode
Definition: stm32f4xx_ll_fmc.h:504
FMC_NAND_InitTypeDef::ECCPageSize
uint32_t ECCPageSize
Definition: stm32f4xx_ll_fmc.h:361
FMC_NAND_InitTypeDef::EccComputation
uint32_t EccComputation
Definition: stm32f4xx_ll_fmc.h:358
FMC_NORSRAM_InitTypeDef::NSBank
uint32_t NSBank
Definition: stm32f4xx_ll_fmc.h:234
FMC_NORSRAM_TimingTypeDef::DataLatency
uint32_t DataLatency
Definition: stm32f4xx_ll_fmc.h:330
FMC_SDRAM_TimingTypeDef::RowCycleDelay
uint32_t RowCycleDelay
Definition: stm32f4xx_ll_fmc.h:482
FMC_NAND_InitTypeDef::NandBank
uint32_t NandBank
Definition: stm32f4xx_ll_fmc.h:349
FMC_SDRAM_InitTypeDef::SDBank
uint32_t SDBank
Definition: stm32f4xx_ll_fmc.h:432
FMC_NAND_InitTypeDef::Waitfeature
uint32_t Waitfeature
Definition: stm32f4xx_ll_fmc.h:352
FMC_SDRAM_InitTypeDef::SDClockPeriod
uint32_t SDClockPeriod
Definition: stm32f4xx_ll_fmc.h:453
FMC_NAND_InitTypeDef::MemoryDataWidth
uint32_t MemoryDataWidth
Definition: stm32f4xx_ll_fmc.h:355
FMC_NORSRAM_InitTypeDef::ContinuousClock
uint32_t ContinuousClock
Definition: stm32f4xx_ll_fmc.h:283
FMC_NAND_InitTypeDef
FMC NAND Configuration Structure definition.
Definition: stm32f4xx_ll_fmc.h:348
FMC_NAND_PCC_TimingTypeDef
FMC NAND Timing parameters structure definition.
Definition: stm32f4xx_ll_fmc.h:379
FMC_NORSRAM_InitTypeDef
FMC NORSRAM Configuration Structure definition.
Definition: stm32f4xx_ll_fmc.h:233
FMC_NORSRAM_TimingTypeDef
FMC NORSRAM Timing parameters structure definition.
Definition: stm32f4xx_ll_fmc.h:302
FMC_PCCARD_InitTypeDef
FMC PCCARD Configuration Structure definition.
Definition: stm32f4xx_ll_fmc.h:412
FMC_SDRAM_CommandTypeDef
SDRAM command parameters structure definition.
Definition: stm32f4xx_ll_fmc.h:503
FMC_SDRAM_InitTypeDef
FMC SDRAM Configuration Structure definition.
Definition: stm32f4xx_ll_fmc.h:431
FMC_SDRAM_TimingTypeDef
FMC SDRAM Timing parameters structure definition.
Definition: stm32f4xx_ll_fmc.h:469
FMC_NAND_CommonSpace_Timing_Init
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
Initializes the FMC_NAND Common space Timing according to the specified parameters in the FMC_NAND_PC...
Definition: stm32f4xx_ll_fmc.c:656
FMC_NAND_Init
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
Initializes the FMC_NAND device according to the specified control parameters in the FMC_NAND_HandleT...
Definition: stm32f4xx_ll_fmc.c:598
FMC_NAND_AttributeSpace_Timing_Init
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
Initializes the FMC_NAND Attribute space Timing according to the specified parameters in the FMC_NAND...
Definition: stm32f4xx_ll_fmc.c:707
FMC_NAND_DeInit
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
DeInitializes the FMC_NAND device.
Definition: stm32f4xx_ll_fmc.c:756
FMC_NAND_ECC_Disable
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
Disables dynamically FMC_NAND ECC feature.
Definition: stm32f4xx_ll_fmc.c:857
FMC_NAND_ECC_Enable
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
Enables dynamically FMC_NAND ECC feature.
Definition: stm32f4xx_ll_fmc.c:824
FMC_NAND_GetECC
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
Disables dynamically FMC_NAND ECC feature.
Definition: stm32f4xx_ll_fmc.c:891
FMC_NORSRAM_DeInit
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
DeInitialize the FMC_NORSRAM peripheral.
Definition: stm32f4xx_ll_fmc.c:361
FMC_NORSRAM_Init
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
Initialize the FMC_NORSRAM device according to the specified control parameters in the FMC_NORSRAM_In...
Definition: stm32f4xx_ll_fmc.c:239
FMC_NORSRAM_Timing_Init
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
Initialize the FMC_NORSRAM Timing according to the specified parameters in the FMC_NORSRAM_TimingType...
Definition: stm32f4xx_ll_fmc.c:398
FMC_NORSRAM_Extended_Timing_Init
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
Initialize the FMC_NORSRAM Extended mode Timing according to the specified parameters in the FMC_NORS...
Definition: stm32f4xx_ll_fmc.c:450
FMC_NORSRAM_WriteOperation_Disable
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
Disables dynamically FMC_NORSRAM write operation.
Definition: stm32f4xx_ll_fmc.c:526
FMC_NORSRAM_WriteOperation_Enable
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
Enables dynamically FMC_NORSRAM write operation.
Definition: stm32f4xx_ll_fmc.c:508
FMC_PCCARD_CommonSpace_Timing_Init
HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
Initializes the FMC_PCCARD Common space Timing according to the specified parameters in the FMC_NAND_...
Definition: stm32f4xx_ll_fmc.c:1025
FMC_PCCARD_AttributeSpace_Timing_Init
HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
Initializes the FMC_PCCARD Attribute space Timing according to the specified parameters in the FMC_NA...
Definition: stm32f4xx_ll_fmc.c:1054
FMC_PCCARD_DeInit
HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
DeInitializes the FMC_PCCARD device.
Definition: stm32f4xx_ll_fmc.c:1110
FMC_PCCARD_Init
HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
Initializes the FMC_PCCARD device according to the specified control parameters in the FMC_PCCARD_Han...
Definition: stm32f4xx_ll_fmc.c:992
FMC_PCCARD_IOSpace_Timing_Init
HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
Initializes the FMC_PCCARD IO space Timing according to the specified parameters in the FMC_NAND_PCC_...
Definition: stm32f4xx_ll_fmc.c:1083
FMC_SDRAM_Timing_Init
HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
Initializes the FMC_SDRAM device timing according to the specified parameters in the FMC_SDRAM_Timing...
Definition: stm32f4xx_ll_fmc.c:1243
FMC_SDRAM_DeInit
HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
DeInitializes the FMC_SDRAM peripheral.
Definition: stm32f4xx_ll_fmc.c:1295
FMC_SDRAM_Init
HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
Initializes the FMC_SDRAM device according to the specified control parameters in the FMC_SDRAM_InitT...
Definition: stm32f4xx_ll_fmc.c:1181
FMC_SDRAM_WriteProtection_Disable
HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
Disables dynamically FMC_SDRAM write protection.
Definition: stm32f4xx_ll_fmc.c:1353
FMC_SDRAM_SetAutoRefreshNumber
HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
Set the Number of consecutive SDRAM Memory auto Refresh commands.
Definition: stm32f4xx_ll_fmc.c:1431
FMC_SDRAM_GetModeStatus
uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)
Returns the indicated FMC SDRAM bank mode status.
Definition: stm32f4xx_ll_fmc.c:1453
FMC_SDRAM_SendCommand
HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
Send Command to the FMC SDRAM bank.
Definition: stm32f4xx_ll_fmc.c:1373
FMC_SDRAM_WriteProtection_Enable
HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
Enables dynamically FMC_SDRAM write protection.
Definition: stm32f4xx_ll_fmc.c:1336
FMC_SDRAM_ProgramRefreshRate
HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
Program the SDRAM Memory Refresh rate.
Definition: stm32f4xx_ll_fmc.c:1413
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.