STM32F4xx_HAL_Driver  1.8.3
stm32f4xx_hal_i2c.c
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1 
300 /* Includes ------------------------------------------------------------------*/
301 #include "stm32f4xx_hal.h"
302 
312 #ifdef HAL_I2C_MODULE_ENABLED
313 
314 /* Private typedef -----------------------------------------------------------*/
315 /* Private define ------------------------------------------------------------*/
319 #define I2C_TIMEOUT_FLAG 35U
320 #define I2C_TIMEOUT_BUSY_FLAG 25U
321 #define I2C_TIMEOUT_STOP_FLAG 5U
322 #define I2C_NO_OPTION_FRAME 0xFFFF0000U
324 /* Private define for @ref PreviousState usage */
325 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
326 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
327 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))
328 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))
329 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))
330 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))
336 /* Private macro -------------------------------------------------------------*/
340 /* Macro to get remaining data to transfer on DMA side */
341 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
345 /* Private variables ---------------------------------------------------------*/
346 /* Private function prototypes -----------------------------------------------*/
347 
351 /* Private functions to handle DMA transfer */
352 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
353 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
354 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
355 
356 static void I2C_ITError(I2C_HandleTypeDef *hi2c);
357 
358 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
359 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
360 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
361 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
362 
363 /* Private functions to handle flags during polling transfer */
364 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
365 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
366 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
367 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
368 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
369 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
370 static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c);
371 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
372 
373 /* Private functions for I2C transfer IRQ handler */
374 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
375 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
376 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
377 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
378 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c);
379 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
380 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
381 
382 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
383 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
384 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
385 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
386 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags);
387 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
388 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
389 
390 static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c);
391 
392 /* Private function to Convert Specific options */
393 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
394 
395 /* Private function to flush DR register */
396 static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c);
401 /* Exported functions --------------------------------------------------------*/
402 
445 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
446 {
447  uint32_t freqrange;
448  uint32_t pclk1;
449 
450  /* Check the I2C handle allocation */
451  if (hi2c == NULL)
452  {
453  return HAL_ERROR;
454  }
455 
456  /* Check the parameters */
457  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
458  assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
459  assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
460  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
461  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
462  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
463  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
464  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
465  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
466 
467  if (hi2c->State == HAL_I2C_STATE_RESET)
468  {
469  /* Allocate lock resource and initialize it */
470  hi2c->Lock = HAL_UNLOCKED;
471 
472 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
473  /* Init the I2C Callback settings */
474  hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
475  hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
476  hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
477  hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
478  hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
479  hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
480  hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
481  hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
482  hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
483  hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
484 
485  if (hi2c->MspInitCallback == NULL)
486  {
487  hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
488  }
489 
490  /* Init the low level hardware : GPIO, CLOCK, NVIC */
491  hi2c->MspInitCallback(hi2c);
492 #else
493  /* Init the low level hardware : GPIO, CLOCK, NVIC */
494  HAL_I2C_MspInit(hi2c);
495 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
496  }
497 
498  hi2c->State = HAL_I2C_STATE_BUSY;
499 
500  /* Disable the selected I2C peripheral */
501  __HAL_I2C_DISABLE(hi2c);
502 
503  /*Reset I2C*/
504  hi2c->Instance->CR1 |= I2C_CR1_SWRST;
505  hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
506 
507  /* Get PCLK1 frequency */
508  pclk1 = HAL_RCC_GetPCLK1Freq();
509 
510  /* Check the minimum allowed PCLK1 frequency */
511  if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
512  {
513  return HAL_ERROR;
514  }
515 
516  /* Calculate frequency range */
517  freqrange = I2C_FREQRANGE(pclk1);
518 
519  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
520  /* Configure I2Cx: Frequency range */
521  MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
522 
523  /*---------------------------- I2Cx TRISE Configuration --------------------*/
524  /* Configure I2Cx: Rise Time */
525  MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
526 
527  /*---------------------------- I2Cx CCR Configuration ----------------------*/
528  /* Configure I2Cx: Speed */
529  MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
530 
531  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
532  /* Configure I2Cx: Generalcall and NoStretch mode */
533  MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
534 
535  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
536  /* Configure I2Cx: Own Address1 and addressing mode */
537  MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
538 
539  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
540  /* Configure I2Cx: Dual mode and Own Address2 */
541  MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
542 
543  /* Enable the selected I2C peripheral */
544  __HAL_I2C_ENABLE(hi2c);
545 
546  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
547  hi2c->State = HAL_I2C_STATE_READY;
548  hi2c->PreviousState = I2C_STATE_NONE;
549  hi2c->Mode = HAL_I2C_MODE_NONE;
550 
551  return HAL_OK;
552 }
553 
560 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
561 {
562  /* Check the I2C handle allocation */
563  if (hi2c == NULL)
564  {
565  return HAL_ERROR;
566  }
567 
568  /* Check the parameters */
569  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
570 
571  hi2c->State = HAL_I2C_STATE_BUSY;
572 
573  /* Disable the I2C Peripheral Clock */
574  __HAL_I2C_DISABLE(hi2c);
575 
576 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
577  if (hi2c->MspDeInitCallback == NULL)
578  {
579  hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
580  }
581 
582  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
583  hi2c->MspDeInitCallback(hi2c);
584 #else
585  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
586  HAL_I2C_MspDeInit(hi2c);
587 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
588 
589  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
590  hi2c->State = HAL_I2C_STATE_RESET;
591  hi2c->PreviousState = I2C_STATE_NONE;
592  hi2c->Mode = HAL_I2C_MODE_NONE;
593 
594  /* Release Lock */
595  __HAL_UNLOCK(hi2c);
596 
597  return HAL_OK;
598 }
599 
606 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
607 {
608  /* Prevent unused argument(s) compilation warning */
609  UNUSED(hi2c);
610 
611  /* NOTE : This function should not be modified, when the callback is needed,
612  the HAL_I2C_MspInit could be implemented in the user file
613  */
614 }
615 
622 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
623 {
624  /* Prevent unused argument(s) compilation warning */
625  UNUSED(hi2c);
626 
627  /* NOTE : This function should not be modified, when the callback is needed,
628  the HAL_I2C_MspDeInit could be implemented in the user file
629  */
630 }
631 
632 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
654 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
655 {
656  HAL_StatusTypeDef status = HAL_OK;
657 
658  if (pCallback == NULL)
659  {
660  /* Update the error code */
661  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
662 
663  return HAL_ERROR;
664  }
665  /* Process locked */
666  __HAL_LOCK(hi2c);
667 
668  if (HAL_I2C_STATE_READY == hi2c->State)
669  {
670  switch (CallbackID)
671  {
672  case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
673  hi2c->MasterTxCpltCallback = pCallback;
674  break;
675 
676  case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
677  hi2c->MasterRxCpltCallback = pCallback;
678  break;
679 
680  case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
681  hi2c->SlaveTxCpltCallback = pCallback;
682  break;
683 
684  case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
685  hi2c->SlaveRxCpltCallback = pCallback;
686  break;
687 
688  case HAL_I2C_LISTEN_COMPLETE_CB_ID :
689  hi2c->ListenCpltCallback = pCallback;
690  break;
691 
692  case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
693  hi2c->MemTxCpltCallback = pCallback;
694  break;
695 
696  case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
697  hi2c->MemRxCpltCallback = pCallback;
698  break;
699 
700  case HAL_I2C_ERROR_CB_ID :
701  hi2c->ErrorCallback = pCallback;
702  break;
703 
704  case HAL_I2C_ABORT_CB_ID :
705  hi2c->AbortCpltCallback = pCallback;
706  break;
707 
708  case HAL_I2C_MSPINIT_CB_ID :
709  hi2c->MspInitCallback = pCallback;
710  break;
711 
712  case HAL_I2C_MSPDEINIT_CB_ID :
713  hi2c->MspDeInitCallback = pCallback;
714  break;
715 
716  default :
717  /* Update the error code */
718  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
719 
720  /* Return error status */
721  status = HAL_ERROR;
722  break;
723  }
724  }
725  else if (HAL_I2C_STATE_RESET == hi2c->State)
726  {
727  switch (CallbackID)
728  {
729  case HAL_I2C_MSPINIT_CB_ID :
730  hi2c->MspInitCallback = pCallback;
731  break;
732 
733  case HAL_I2C_MSPDEINIT_CB_ID :
734  hi2c->MspDeInitCallback = pCallback;
735  break;
736 
737  default :
738  /* Update the error code */
739  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
740 
741  /* Return error status */
742  status = HAL_ERROR;
743  break;
744  }
745  }
746  else
747  {
748  /* Update the error code */
749  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
750 
751  /* Return error status */
752  status = HAL_ERROR;
753  }
754 
755  /* Release Lock */
756  __HAL_UNLOCK(hi2c);
757  return status;
758 }
759 
781 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
782 {
783  HAL_StatusTypeDef status = HAL_OK;
784 
785  /* Process locked */
786  __HAL_LOCK(hi2c);
787 
788  if (HAL_I2C_STATE_READY == hi2c->State)
789  {
790  switch (CallbackID)
791  {
792  case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
793  hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
794  break;
795 
796  case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
797  hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
798  break;
799 
800  case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
801  hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
802  break;
803 
804  case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
805  hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
806  break;
807 
808  case HAL_I2C_LISTEN_COMPLETE_CB_ID :
809  hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
810  break;
811 
812  case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
813  hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
814  break;
815 
816  case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
817  hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
818  break;
819 
820  case HAL_I2C_ERROR_CB_ID :
821  hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
822  break;
823 
824  case HAL_I2C_ABORT_CB_ID :
825  hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
826  break;
827 
828  case HAL_I2C_MSPINIT_CB_ID :
829  hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
830  break;
831 
832  case HAL_I2C_MSPDEINIT_CB_ID :
833  hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
834  break;
835 
836  default :
837  /* Update the error code */
838  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
839 
840  /* Return error status */
841  status = HAL_ERROR;
842  break;
843  }
844  }
845  else if (HAL_I2C_STATE_RESET == hi2c->State)
846  {
847  switch (CallbackID)
848  {
849  case HAL_I2C_MSPINIT_CB_ID :
850  hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
851  break;
852 
853  case HAL_I2C_MSPDEINIT_CB_ID :
854  hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
855  break;
856 
857  default :
858  /* Update the error code */
859  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
860 
861  /* Return error status */
862  status = HAL_ERROR;
863  break;
864  }
865  }
866  else
867  {
868  /* Update the error code */
869  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
870 
871  /* Return error status */
872  status = HAL_ERROR;
873  }
874 
875  /* Release Lock */
876  __HAL_UNLOCK(hi2c);
877  return status;
878 }
879 
888 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
889 {
890  HAL_StatusTypeDef status = HAL_OK;
891 
892  if (pCallback == NULL)
893  {
894  /* Update the error code */
895  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
896 
897  return HAL_ERROR;
898  }
899  /* Process locked */
900  __HAL_LOCK(hi2c);
901 
902  if (HAL_I2C_STATE_READY == hi2c->State)
903  {
904  hi2c->AddrCallback = pCallback;
905  }
906  else
907  {
908  /* Update the error code */
909  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
910 
911  /* Return error status */
912  status = HAL_ERROR;
913  }
914 
915  /* Release Lock */
916  __HAL_UNLOCK(hi2c);
917  return status;
918 }
919 
927 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
928 {
929  HAL_StatusTypeDef status = HAL_OK;
930 
931  /* Process locked */
932  __HAL_LOCK(hi2c);
933 
934  if (HAL_I2C_STATE_READY == hi2c->State)
935  {
936  hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
937  }
938  else
939  {
940  /* Update the error code */
941  hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
942 
943  /* Return error status */
944  status = HAL_ERROR;
945  }
946 
947  /* Release Lock */
948  __HAL_UNLOCK(hi2c);
949  return status;
950 }
951 
952 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
953 
959 static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c)
960 {
961  /* Write a dummy data in DR to clear TXE flag */
962  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) != RESET)
963  {
964  hi2c->Instance->DR = 0x00U;
965  }
966 }
967 
1056 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1057 {
1058  /* Init tickstart for timeout management*/
1059  uint32_t tickstart = HAL_GetTick();
1060 
1061  if (hi2c->State == HAL_I2C_STATE_READY)
1062  {
1063  /* Wait until BUSY flag is reset */
1064  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
1065  {
1066  return HAL_BUSY;
1067  }
1068 
1069  /* Process Locked */
1070  __HAL_LOCK(hi2c);
1071 
1072  /* Check if the I2C is already enabled */
1073  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1074  {
1075  /* Enable I2C peripheral */
1076  __HAL_I2C_ENABLE(hi2c);
1077  }
1078 
1079  /* Disable Pos */
1080  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1081 
1082  hi2c->State = HAL_I2C_STATE_BUSY_TX;
1083  hi2c->Mode = HAL_I2C_MODE_MASTER;
1084  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1085 
1086  /* Prepare transfer parameters */
1087  hi2c->pBuffPtr = pData;
1088  hi2c->XferCount = Size;
1089  hi2c->XferSize = hi2c->XferCount;
1090  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1091 
1092  /* Send Slave Address */
1093  if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
1094  {
1095  return HAL_ERROR;
1096  }
1097 
1098  /* Clear ADDR flag */
1099  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1100 
1101  while (hi2c->XferSize > 0U)
1102  {
1103  /* Wait until TXE flag is set */
1104  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1105  {
1106  if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1107  {
1108  /* Generate Stop */
1109  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1110  }
1111  return HAL_ERROR;
1112  }
1113 
1114  /* Write data to DR */
1115  hi2c->Instance->DR = *hi2c->pBuffPtr;
1116 
1117  /* Increment Buffer pointer */
1118  hi2c->pBuffPtr++;
1119 
1120  /* Update counter */
1121  hi2c->XferCount--;
1122  hi2c->XferSize--;
1123 
1124  if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1125  {
1126  /* Write data to DR */
1127  hi2c->Instance->DR = *hi2c->pBuffPtr;
1128 
1129  /* Increment Buffer pointer */
1130  hi2c->pBuffPtr++;
1131 
1132  /* Update counter */
1133  hi2c->XferCount--;
1134  hi2c->XferSize--;
1135  }
1136 
1137  /* Wait until BTF flag is set */
1138  if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1139  {
1140  if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1141  {
1142  /* Generate Stop */
1143  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1144  }
1145  return HAL_ERROR;
1146  }
1147  }
1148 
1149  /* Generate Stop */
1150  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1151 
1152  hi2c->State = HAL_I2C_STATE_READY;
1153  hi2c->Mode = HAL_I2C_MODE_NONE;
1154 
1155  /* Process Unlocked */
1156  __HAL_UNLOCK(hi2c);
1157 
1158  return HAL_OK;
1159  }
1160  else
1161  {
1162  return HAL_BUSY;
1163  }
1164 }
1165 
1177 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1178 {
1179  /* Init tickstart for timeout management*/
1180  uint32_t tickstart = HAL_GetTick();
1181 
1182  if (hi2c->State == HAL_I2C_STATE_READY)
1183  {
1184  /* Wait until BUSY flag is reset */
1185  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
1186  {
1187  return HAL_BUSY;
1188  }
1189 
1190  /* Process Locked */
1191  __HAL_LOCK(hi2c);
1192 
1193  /* Check if the I2C is already enabled */
1194  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1195  {
1196  /* Enable I2C peripheral */
1197  __HAL_I2C_ENABLE(hi2c);
1198  }
1199 
1200  /* Disable Pos */
1201  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1202 
1203  hi2c->State = HAL_I2C_STATE_BUSY_RX;
1204  hi2c->Mode = HAL_I2C_MODE_MASTER;
1205  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1206 
1207  /* Prepare transfer parameters */
1208  hi2c->pBuffPtr = pData;
1209  hi2c->XferCount = Size;
1210  hi2c->XferSize = hi2c->XferCount;
1211  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1212 
1213  /* Send Slave Address */
1214  if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
1215  {
1216  return HAL_ERROR;
1217  }
1218 
1219  if (hi2c->XferSize == 0U)
1220  {
1221  /* Clear ADDR flag */
1222  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1223 
1224  /* Generate Stop */
1225  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1226  }
1227  else if (hi2c->XferSize == 1U)
1228  {
1229  /* Disable Acknowledge */
1230  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1231 
1232  /* Clear ADDR flag */
1233  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1234 
1235  /* Generate Stop */
1236  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1237  }
1238  else if (hi2c->XferSize == 2U)
1239  {
1240  /* Disable Acknowledge */
1241  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1242 
1243  /* Enable Pos */
1244  SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1245 
1246  /* Clear ADDR flag */
1247  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1248  }
1249  else
1250  {
1251  /* Enable Acknowledge */
1252  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1253 
1254  /* Clear ADDR flag */
1255  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1256  }
1257 
1258  while (hi2c->XferSize > 0U)
1259  {
1260  if (hi2c->XferSize <= 3U)
1261  {
1262  /* One byte */
1263  if (hi2c->XferSize == 1U)
1264  {
1265  /* Wait until RXNE flag is set */
1266  if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1267  {
1268  return HAL_ERROR;
1269  }
1270 
1271  /* Read data from DR */
1272  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1273 
1274  /* Increment Buffer pointer */
1275  hi2c->pBuffPtr++;
1276 
1277  /* Update counter */
1278  hi2c->XferSize--;
1279  hi2c->XferCount--;
1280  }
1281  /* Two bytes */
1282  else if (hi2c->XferSize == 2U)
1283  {
1284  /* Wait until BTF flag is set */
1285  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1286  {
1287  return HAL_ERROR;
1288  }
1289 
1290  /* Generate Stop */
1291  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1292 
1293  /* Read data from DR */
1294  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1295 
1296  /* Increment Buffer pointer */
1297  hi2c->pBuffPtr++;
1298 
1299  /* Update counter */
1300  hi2c->XferSize--;
1301  hi2c->XferCount--;
1302 
1303  /* Read data from DR */
1304  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1305 
1306  /* Increment Buffer pointer */
1307  hi2c->pBuffPtr++;
1308 
1309  /* Update counter */
1310  hi2c->XferSize--;
1311  hi2c->XferCount--;
1312  }
1313  /* 3 Last bytes */
1314  else
1315  {
1316  /* Wait until BTF flag is set */
1317  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1318  {
1319  return HAL_ERROR;
1320  }
1321 
1322  /* Disable Acknowledge */
1323  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1324 
1325  /* Read data from DR */
1326  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1327 
1328  /* Increment Buffer pointer */
1329  hi2c->pBuffPtr++;
1330 
1331  /* Update counter */
1332  hi2c->XferSize--;
1333  hi2c->XferCount--;
1334 
1335  /* Wait until BTF flag is set */
1336  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1337  {
1338  return HAL_ERROR;
1339  }
1340 
1341  /* Generate Stop */
1342  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1343 
1344  /* Read data from DR */
1345  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1346 
1347  /* Increment Buffer pointer */
1348  hi2c->pBuffPtr++;
1349 
1350  /* Update counter */
1351  hi2c->XferSize--;
1352  hi2c->XferCount--;
1353 
1354  /* Read data from DR */
1355  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1356 
1357  /* Increment Buffer pointer */
1358  hi2c->pBuffPtr++;
1359 
1360  /* Update counter */
1361  hi2c->XferSize--;
1362  hi2c->XferCount--;
1363  }
1364  }
1365  else
1366  {
1367  /* Wait until RXNE flag is set */
1368  if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1369  {
1370  return HAL_ERROR;
1371  }
1372 
1373  /* Read data from DR */
1374  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1375 
1376  /* Increment Buffer pointer */
1377  hi2c->pBuffPtr++;
1378 
1379  /* Update counter */
1380  hi2c->XferSize--;
1381  hi2c->XferCount--;
1382 
1383  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
1384  {
1385 
1386  if (hi2c->XferSize == 3U)
1387  {
1388  /* Disable Acknowledge */
1389  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1390  }
1391 
1392  /* Read data from DR */
1393  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1394 
1395  /* Increment Buffer pointer */
1396  hi2c->pBuffPtr++;
1397 
1398  /* Update counter */
1399  hi2c->XferSize--;
1400  hi2c->XferCount--;
1401  }
1402  }
1403  }
1404 
1405  hi2c->State = HAL_I2C_STATE_READY;
1406  hi2c->Mode = HAL_I2C_MODE_NONE;
1407 
1408  /* Process Unlocked */
1409  __HAL_UNLOCK(hi2c);
1410 
1411  return HAL_OK;
1412  }
1413  else
1414  {
1415  return HAL_BUSY;
1416  }
1417 }
1418 
1428 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1429 {
1430  /* Init tickstart for timeout management*/
1431  uint32_t tickstart = HAL_GetTick();
1432 
1433  if (hi2c->State == HAL_I2C_STATE_READY)
1434  {
1435  if ((pData == NULL) || (Size == 0U))
1436  {
1437  return HAL_ERROR;
1438  }
1439 
1440  /* Process Locked */
1441  __HAL_LOCK(hi2c);
1442 
1443  /* Check if the I2C is already enabled */
1444  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1445  {
1446  /* Enable I2C peripheral */
1447  __HAL_I2C_ENABLE(hi2c);
1448  }
1449 
1450  /* Disable Pos */
1451  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1452 
1453  hi2c->State = HAL_I2C_STATE_BUSY_TX;
1454  hi2c->Mode = HAL_I2C_MODE_SLAVE;
1455  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1456 
1457  /* Prepare transfer parameters */
1458  hi2c->pBuffPtr = pData;
1459  hi2c->XferCount = Size;
1460  hi2c->XferSize = hi2c->XferCount;
1461  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1462 
1463  /* Enable Address Acknowledge */
1464  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1465 
1466  /* Wait until ADDR flag is set */
1467  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1468  {
1469  return HAL_ERROR;
1470  }
1471 
1472  /* Clear ADDR flag */
1473  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1474 
1475  /* If 10bit addressing mode is selected */
1476  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1477  {
1478  /* Wait until ADDR flag is set */
1479  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1480  {
1481  return HAL_ERROR;
1482  }
1483 
1484  /* Clear ADDR flag */
1485  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1486  }
1487 
1488  while (hi2c->XferSize > 0U)
1489  {
1490  /* Wait until TXE flag is set */
1491  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1492  {
1493  /* Disable Address Acknowledge */
1494  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1495 
1496  return HAL_ERROR;
1497  }
1498 
1499  /* Write data to DR */
1500  hi2c->Instance->DR = *hi2c->pBuffPtr;
1501 
1502  /* Increment Buffer pointer */
1503  hi2c->pBuffPtr++;
1504 
1505  /* Update counter */
1506  hi2c->XferCount--;
1507  hi2c->XferSize--;
1508 
1509  if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1510  {
1511  /* Write data to DR */
1512  hi2c->Instance->DR = *hi2c->pBuffPtr;
1513 
1514  /* Increment Buffer pointer */
1515  hi2c->pBuffPtr++;
1516 
1517  /* Update counter */
1518  hi2c->XferCount--;
1519  hi2c->XferSize--;
1520  }
1521  }
1522 
1523  /* Wait until AF flag is set */
1524  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1525  {
1526  return HAL_ERROR;
1527  }
1528 
1529  /* Clear AF flag */
1530  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1531 
1532  /* Disable Address Acknowledge */
1533  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1534 
1535  hi2c->State = HAL_I2C_STATE_READY;
1536  hi2c->Mode = HAL_I2C_MODE_NONE;
1537 
1538  /* Process Unlocked */
1539  __HAL_UNLOCK(hi2c);
1540 
1541  return HAL_OK;
1542  }
1543  else
1544  {
1545  return HAL_BUSY;
1546  }
1547 }
1548 
1558 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1559 {
1560  /* Init tickstart for timeout management*/
1561  uint32_t tickstart = HAL_GetTick();
1562 
1563  if (hi2c->State == HAL_I2C_STATE_READY)
1564  {
1565  if ((pData == NULL) || (Size == (uint16_t)0))
1566  {
1567  return HAL_ERROR;
1568  }
1569 
1570  /* Process Locked */
1571  __HAL_LOCK(hi2c);
1572 
1573  /* Check if the I2C is already enabled */
1574  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1575  {
1576  /* Enable I2C peripheral */
1577  __HAL_I2C_ENABLE(hi2c);
1578  }
1579 
1580  /* Disable Pos */
1581  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1582 
1583  hi2c->State = HAL_I2C_STATE_BUSY_RX;
1584  hi2c->Mode = HAL_I2C_MODE_SLAVE;
1585  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1586 
1587  /* Prepare transfer parameters */
1588  hi2c->pBuffPtr = pData;
1589  hi2c->XferCount = Size;
1590  hi2c->XferSize = hi2c->XferCount;
1591  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1592 
1593  /* Enable Address Acknowledge */
1594  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1595 
1596  /* Wait until ADDR flag is set */
1597  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1598  {
1599  return HAL_ERROR;
1600  }
1601 
1602  /* Clear ADDR flag */
1603  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1604 
1605  while (hi2c->XferSize > 0U)
1606  {
1607  /* Wait until RXNE flag is set */
1608  if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1609  {
1610  /* Disable Address Acknowledge */
1611  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1612 
1613  return HAL_ERROR;
1614  }
1615 
1616  /* Read data from DR */
1617  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1618 
1619  /* Increment Buffer pointer */
1620  hi2c->pBuffPtr++;
1621 
1622  /* Update counter */
1623  hi2c->XferSize--;
1624  hi2c->XferCount--;
1625 
1626  if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1627  {
1628  /* Read data from DR */
1629  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1630 
1631  /* Increment Buffer pointer */
1632  hi2c->pBuffPtr++;
1633 
1634  /* Update counter */
1635  hi2c->XferSize--;
1636  hi2c->XferCount--;
1637  }
1638  }
1639 
1640  /* Wait until STOP flag is set */
1641  if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1642  {
1643  /* Disable Address Acknowledge */
1644  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1645 
1646  return HAL_ERROR;
1647  }
1648 
1649  /* Clear STOP flag */
1650  __HAL_I2C_CLEAR_STOPFLAG(hi2c);
1651 
1652  /* Disable Address Acknowledge */
1653  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1654 
1655  hi2c->State = HAL_I2C_STATE_READY;
1656  hi2c->Mode = HAL_I2C_MODE_NONE;
1657 
1658  /* Process Unlocked */
1659  __HAL_UNLOCK(hi2c);
1660 
1661  return HAL_OK;
1662  }
1663  else
1664  {
1665  return HAL_BUSY;
1666  }
1667 }
1668 
1679 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1680 {
1681  __IO uint32_t count = 0U;
1682 
1683  if (hi2c->State == HAL_I2C_STATE_READY)
1684  {
1685  /* Wait until BUSY flag is reset */
1686  count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1687  do
1688  {
1689  count--;
1690  if (count == 0U)
1691  {
1692  hi2c->PreviousState = I2C_STATE_NONE;
1693  hi2c->State = HAL_I2C_STATE_READY;
1694  hi2c->Mode = HAL_I2C_MODE_NONE;
1695  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1696 
1697  return HAL_BUSY;
1698  }
1699  }
1700  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1701 
1702  /* Process Locked */
1703  __HAL_LOCK(hi2c);
1704 
1705  /* Check if the I2C is already enabled */
1706  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1707  {
1708  /* Enable I2C peripheral */
1709  __HAL_I2C_ENABLE(hi2c);
1710  }
1711 
1712  /* Disable Pos */
1713  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1714 
1715  hi2c->State = HAL_I2C_STATE_BUSY_TX;
1716  hi2c->Mode = HAL_I2C_MODE_MASTER;
1717  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1718 
1719  /* Prepare transfer parameters */
1720  hi2c->pBuffPtr = pData;
1721  hi2c->XferCount = Size;
1722  hi2c->XferSize = hi2c->XferCount;
1723  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1724  hi2c->Devaddress = DevAddress;
1725 
1726  /* Process Unlocked */
1727  __HAL_UNLOCK(hi2c);
1728 
1729  /* Note : The I2C interrupts must be enabled after unlocking current process
1730  to avoid the risk of I2C interrupt handle execution before current
1731  process unlock */
1732  /* Enable EVT, BUF and ERR interrupt */
1733  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1734 
1735  /* Generate Start */
1736  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1737 
1738  return HAL_OK;
1739  }
1740  else
1741  {
1742  return HAL_BUSY;
1743  }
1744 }
1745 
1756 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1757 {
1758  __IO uint32_t count = 0U;
1759 
1760  if (hi2c->State == HAL_I2C_STATE_READY)
1761  {
1762  /* Wait until BUSY flag is reset */
1763  count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1764  do
1765  {
1766  count--;
1767  if (count == 0U)
1768  {
1769  hi2c->PreviousState = I2C_STATE_NONE;
1770  hi2c->State = HAL_I2C_STATE_READY;
1771  hi2c->Mode = HAL_I2C_MODE_NONE;
1772  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1773 
1774  return HAL_BUSY;
1775  }
1776  }
1777  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1778 
1779  /* Process Locked */
1780  __HAL_LOCK(hi2c);
1781 
1782  /* Check if the I2C is already enabled */
1783  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1784  {
1785  /* Enable I2C peripheral */
1786  __HAL_I2C_ENABLE(hi2c);
1787  }
1788 
1789  /* Disable Pos */
1790  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1791 
1792  hi2c->State = HAL_I2C_STATE_BUSY_RX;
1793  hi2c->Mode = HAL_I2C_MODE_MASTER;
1794  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1795 
1796  /* Prepare transfer parameters */
1797  hi2c->pBuffPtr = pData;
1798  hi2c->XferCount = Size;
1799  hi2c->XferSize = hi2c->XferCount;
1800  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1801  hi2c->Devaddress = DevAddress;
1802 
1803 
1804  /* Process Unlocked */
1805  __HAL_UNLOCK(hi2c);
1806 
1807  /* Note : The I2C interrupts must be enabled after unlocking current process
1808  to avoid the risk of I2C interrupt handle execution before current
1809  process unlock */
1810 
1811  /* Enable EVT, BUF and ERR interrupt */
1812  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1813 
1814  /* Enable Acknowledge */
1815  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1816 
1817  /* Generate Start */
1818  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1819 
1820  return HAL_OK;
1821  }
1822  else
1823  {
1824  return HAL_BUSY;
1825  }
1826 }
1827 
1836 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1837 {
1838 
1839  if (hi2c->State == HAL_I2C_STATE_READY)
1840  {
1841  if ((pData == NULL) || (Size == 0U))
1842  {
1843  return HAL_ERROR;
1844  }
1845 
1846  /* Process Locked */
1847  __HAL_LOCK(hi2c);
1848 
1849  /* Check if the I2C is already enabled */
1850  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1851  {
1852  /* Enable I2C peripheral */
1853  __HAL_I2C_ENABLE(hi2c);
1854  }
1855 
1856  /* Disable Pos */
1857  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1858 
1859  hi2c->State = HAL_I2C_STATE_BUSY_TX;
1860  hi2c->Mode = HAL_I2C_MODE_SLAVE;
1861  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1862 
1863  /* Prepare transfer parameters */
1864  hi2c->pBuffPtr = pData;
1865  hi2c->XferCount = Size;
1866  hi2c->XferSize = hi2c->XferCount;
1867  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1868 
1869  /* Enable Address Acknowledge */
1870  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1871 
1872  /* Process Unlocked */
1873  __HAL_UNLOCK(hi2c);
1874 
1875  /* Note : The I2C interrupts must be enabled after unlocking current process
1876  to avoid the risk of I2C interrupt handle execution before current
1877  process unlock */
1878 
1879  /* Enable EVT, BUF and ERR interrupt */
1880  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1881 
1882  return HAL_OK;
1883  }
1884  else
1885  {
1886  return HAL_BUSY;
1887  }
1888 }
1889 
1898 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1899 {
1900 
1901  if (hi2c->State == HAL_I2C_STATE_READY)
1902  {
1903  if ((pData == NULL) || (Size == 0U))
1904  {
1905  return HAL_ERROR;
1906  }
1907 
1908  /* Process Locked */
1909  __HAL_LOCK(hi2c);
1910 
1911  /* Check if the I2C is already enabled */
1912  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1913  {
1914  /* Enable I2C peripheral */
1915  __HAL_I2C_ENABLE(hi2c);
1916  }
1917 
1918  /* Disable Pos */
1919  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1920 
1921  hi2c->State = HAL_I2C_STATE_BUSY_RX;
1922  hi2c->Mode = HAL_I2C_MODE_SLAVE;
1923  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1924 
1925  /* Prepare transfer parameters */
1926  hi2c->pBuffPtr = pData;
1927  hi2c->XferCount = Size;
1928  hi2c->XferSize = hi2c->XferCount;
1929  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1930 
1931  /* Enable Address Acknowledge */
1932  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1933 
1934  /* Process Unlocked */
1935  __HAL_UNLOCK(hi2c);
1936 
1937  /* Note : The I2C interrupts must be enabled after unlocking current process
1938  to avoid the risk of I2C interrupt handle execution before current
1939  process unlock */
1940 
1941  /* Enable EVT, BUF and ERR interrupt */
1942  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1943 
1944  return HAL_OK;
1945  }
1946  else
1947  {
1948  return HAL_BUSY;
1949  }
1950 }
1951 
1962 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1963 {
1964  __IO uint32_t count = 0U;
1965  HAL_StatusTypeDef dmaxferstatus;
1966 
1967  if (hi2c->State == HAL_I2C_STATE_READY)
1968  {
1969  /* Wait until BUSY flag is reset */
1970  count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1971  do
1972  {
1973  count--;
1974  if (count == 0U)
1975  {
1976  hi2c->PreviousState = I2C_STATE_NONE;
1977  hi2c->State = HAL_I2C_STATE_READY;
1978  hi2c->Mode = HAL_I2C_MODE_NONE;
1979  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1980 
1981  return HAL_BUSY;
1982  }
1983  }
1984  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1985 
1986  /* Process Locked */
1987  __HAL_LOCK(hi2c);
1988 
1989  /* Check if the I2C is already enabled */
1990  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1991  {
1992  /* Enable I2C peripheral */
1993  __HAL_I2C_ENABLE(hi2c);
1994  }
1995 
1996  /* Disable Pos */
1997  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1998 
1999  hi2c->State = HAL_I2C_STATE_BUSY_TX;
2000  hi2c->Mode = HAL_I2C_MODE_MASTER;
2001  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2002 
2003  /* Prepare transfer parameters */
2004  hi2c->pBuffPtr = pData;
2005  hi2c->XferCount = Size;
2006  hi2c->XferSize = hi2c->XferCount;
2007  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2008  hi2c->Devaddress = DevAddress;
2009 
2010  if (hi2c->XferSize > 0U)
2011  {
2012  if (hi2c->hdmatx != NULL)
2013  {
2014  /* Set the I2C DMA transfer complete callback */
2015  hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
2016 
2017  /* Set the DMA error callback */
2018  hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2019 
2020  /* Set the unused DMA callbacks to NULL */
2021  hi2c->hdmatx->XferHalfCpltCallback = NULL;
2022  hi2c->hdmatx->XferM1CpltCallback = NULL;
2023  hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
2024  hi2c->hdmatx->XferAbortCallback = NULL;
2025 
2026  /* Enable the DMA stream */
2027  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2028  }
2029  else
2030  {
2031  /* Update I2C state */
2032  hi2c->State = HAL_I2C_STATE_READY;
2033  hi2c->Mode = HAL_I2C_MODE_NONE;
2034 
2035  /* Update I2C error code */
2036  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2037 
2038  /* Process Unlocked */
2039  __HAL_UNLOCK(hi2c);
2040 
2041  return HAL_ERROR;
2042  }
2043 
2044  if (dmaxferstatus == HAL_OK)
2045  {
2046  /* Process Unlocked */
2047  __HAL_UNLOCK(hi2c);
2048 
2049  /* Note : The I2C interrupts must be enabled after unlocking current process
2050  to avoid the risk of I2C interrupt handle execution before current
2051  process unlock */
2052 
2053  /* Enable EVT and ERR interrupt */
2054  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2055 
2056  /* Enable DMA Request */
2057  SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2058 
2059  /* Enable Acknowledge */
2060  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2061 
2062  /* Generate Start */
2063  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2064  }
2065  else
2066  {
2067  /* Update I2C state */
2068  hi2c->State = HAL_I2C_STATE_READY;
2069  hi2c->Mode = HAL_I2C_MODE_NONE;
2070 
2071  /* Update I2C error code */
2072  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2073 
2074  /* Process Unlocked */
2075  __HAL_UNLOCK(hi2c);
2076 
2077  return HAL_ERROR;
2078  }
2079  }
2080  else
2081  {
2082  /* Enable Acknowledge */
2083  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2084 
2085  /* Generate Start */
2086  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2087 
2088  /* Process Unlocked */
2089  __HAL_UNLOCK(hi2c);
2090 
2091  /* Note : The I2C interrupts must be enabled after unlocking current process
2092  to avoid the risk of I2C interrupt handle execution before current
2093  process unlock */
2094 
2095  /* Enable EVT, BUF and ERR interrupt */
2096  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2097  }
2098 
2099  return HAL_OK;
2100  }
2101  else
2102  {
2103  return HAL_BUSY;
2104  }
2105 }
2106 
2117 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
2118 {
2119  __IO uint32_t count = 0U;
2120  HAL_StatusTypeDef dmaxferstatus;
2121 
2122  if (hi2c->State == HAL_I2C_STATE_READY)
2123  {
2124  /* Wait until BUSY flag is reset */
2125  count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2126  do
2127  {
2128  count--;
2129  if (count == 0U)
2130  {
2131  hi2c->PreviousState = I2C_STATE_NONE;
2132  hi2c->State = HAL_I2C_STATE_READY;
2133  hi2c->Mode = HAL_I2C_MODE_NONE;
2134  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2135 
2136  return HAL_BUSY;
2137  }
2138  }
2139  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2140 
2141  /* Process Locked */
2142  __HAL_LOCK(hi2c);
2143 
2144  /* Check if the I2C is already enabled */
2145  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2146  {
2147  /* Enable I2C peripheral */
2148  __HAL_I2C_ENABLE(hi2c);
2149  }
2150 
2151  /* Disable Pos */
2152  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2153 
2154  hi2c->State = HAL_I2C_STATE_BUSY_RX;
2155  hi2c->Mode = HAL_I2C_MODE_MASTER;
2156  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2157 
2158  /* Prepare transfer parameters */
2159  hi2c->pBuffPtr = pData;
2160  hi2c->XferCount = Size;
2161  hi2c->XferSize = hi2c->XferCount;
2162  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2163  hi2c->Devaddress = DevAddress;
2164 
2165  if (hi2c->XferSize > 0U)
2166  {
2167  if (hi2c->hdmarx != NULL)
2168  {
2169  /* Set the I2C DMA transfer complete callback */
2170  hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2171 
2172  /* Set the DMA error callback */
2173  hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2174 
2175  /* Set the unused DMA callbacks to NULL */
2176  hi2c->hdmarx->XferHalfCpltCallback = NULL;
2177  hi2c->hdmarx->XferM1CpltCallback = NULL;
2178  hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
2179  hi2c->hdmarx->XferAbortCallback = NULL;
2180 
2181  /* Enable the DMA stream */
2182  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2183  }
2184  else
2185  {
2186  /* Update I2C state */
2187  hi2c->State = HAL_I2C_STATE_READY;
2188  hi2c->Mode = HAL_I2C_MODE_NONE;
2189 
2190  /* Update I2C error code */
2191  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2192 
2193  /* Process Unlocked */
2194  __HAL_UNLOCK(hi2c);
2195 
2196  return HAL_ERROR;
2197  }
2198 
2199  if (dmaxferstatus == HAL_OK)
2200  {
2201  /* Enable Acknowledge */
2202  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2203 
2204  /* Generate Start */
2205  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2206 
2207  /* Process Unlocked */
2208  __HAL_UNLOCK(hi2c);
2209 
2210  /* Note : The I2C interrupts must be enabled after unlocking current process
2211  to avoid the risk of I2C interrupt handle execution before current
2212  process unlock */
2213 
2214  /* Enable EVT and ERR interrupt */
2215  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2216 
2217  /* Enable DMA Request */
2218  SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2219  }
2220  else
2221  {
2222  /* Update I2C state */
2223  hi2c->State = HAL_I2C_STATE_READY;
2224  hi2c->Mode = HAL_I2C_MODE_NONE;
2225 
2226  /* Update I2C error code */
2227  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2228 
2229  /* Process Unlocked */
2230  __HAL_UNLOCK(hi2c);
2231 
2232  return HAL_ERROR;
2233  }
2234  }
2235  else
2236  {
2237  /* Process Unlocked */
2238  __HAL_UNLOCK(hi2c);
2239 
2240  /* Note : The I2C interrupts must be enabled after unlocking current process
2241  to avoid the risk of I2C interrupt handle execution before current
2242  process unlock */
2243 
2244  /* Enable EVT, BUF and ERR interrupt */
2245  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2246 
2247  /* Enable Acknowledge */
2248  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2249 
2250  /* Generate Start */
2251  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2252  }
2253 
2254  return HAL_OK;
2255  }
2256  else
2257  {
2258  return HAL_BUSY;
2259  }
2260 }
2261 
2270 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2271 {
2272  HAL_StatusTypeDef dmaxferstatus;
2273 
2274  if (hi2c->State == HAL_I2C_STATE_READY)
2275  {
2276  if ((pData == NULL) || (Size == 0U))
2277  {
2278  return HAL_ERROR;
2279  }
2280 
2281  /* Process Locked */
2282  __HAL_LOCK(hi2c);
2283 
2284  /* Check if the I2C is already enabled */
2285  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2286  {
2287  /* Enable I2C peripheral */
2288  __HAL_I2C_ENABLE(hi2c);
2289  }
2290 
2291  /* Disable Pos */
2292  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2293 
2294  hi2c->State = HAL_I2C_STATE_BUSY_TX;
2295  hi2c->Mode = HAL_I2C_MODE_SLAVE;
2296  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2297 
2298  /* Prepare transfer parameters */
2299  hi2c->pBuffPtr = pData;
2300  hi2c->XferCount = Size;
2301  hi2c->XferSize = hi2c->XferCount;
2302  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2303 
2304  if (hi2c->hdmatx != NULL)
2305  {
2306  /* Set the I2C DMA transfer complete callback */
2307  hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
2308 
2309  /* Set the DMA error callback */
2310  hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2311 
2312  /* Set the unused DMA callbacks to NULL */
2313  hi2c->hdmatx->XferHalfCpltCallback = NULL;
2314  hi2c->hdmatx->XferM1CpltCallback = NULL;
2315  hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
2316  hi2c->hdmatx->XferAbortCallback = NULL;
2317 
2318  /* Enable the DMA stream */
2319  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2320  }
2321  else
2322  {
2323  /* Update I2C state */
2324  hi2c->State = HAL_I2C_STATE_LISTEN;
2325  hi2c->Mode = HAL_I2C_MODE_NONE;
2326 
2327  /* Update I2C error code */
2328  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2329 
2330  /* Process Unlocked */
2331  __HAL_UNLOCK(hi2c);
2332 
2333  return HAL_ERROR;
2334  }
2335 
2336  if (dmaxferstatus == HAL_OK)
2337  {
2338  /* Enable Address Acknowledge */
2339  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2340 
2341  /* Process Unlocked */
2342  __HAL_UNLOCK(hi2c);
2343 
2344  /* Note : The I2C interrupts must be enabled after unlocking current process
2345  to avoid the risk of I2C interrupt handle execution before current
2346  process unlock */
2347  /* Enable EVT and ERR interrupt */
2348  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2349 
2350  /* Enable DMA Request */
2351  hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
2352 
2353  return HAL_OK;
2354  }
2355  else
2356  {
2357  /* Update I2C state */
2358  hi2c->State = HAL_I2C_STATE_READY;
2359  hi2c->Mode = HAL_I2C_MODE_NONE;
2360 
2361  /* Update I2C error code */
2362  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2363 
2364  /* Process Unlocked */
2365  __HAL_UNLOCK(hi2c);
2366 
2367  return HAL_ERROR;
2368  }
2369  }
2370  else
2371  {
2372  return HAL_BUSY;
2373  }
2374 }
2375 
2384 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2385 {
2386  HAL_StatusTypeDef dmaxferstatus;
2387 
2388  if (hi2c->State == HAL_I2C_STATE_READY)
2389  {
2390  if ((pData == NULL) || (Size == 0U))
2391  {
2392  return HAL_ERROR;
2393  }
2394 
2395  /* Process Locked */
2396  __HAL_LOCK(hi2c);
2397 
2398  /* Check if the I2C is already enabled */
2399  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2400  {
2401  /* Enable I2C peripheral */
2402  __HAL_I2C_ENABLE(hi2c);
2403  }
2404 
2405  /* Disable Pos */
2406  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2407 
2408  hi2c->State = HAL_I2C_STATE_BUSY_RX;
2409  hi2c->Mode = HAL_I2C_MODE_SLAVE;
2410  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2411 
2412  /* Prepare transfer parameters */
2413  hi2c->pBuffPtr = pData;
2414  hi2c->XferCount = Size;
2415  hi2c->XferSize = hi2c->XferCount;
2416  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2417 
2418  if (hi2c->hdmarx != NULL)
2419  {
2420  /* Set the I2C DMA transfer complete callback */
2421  hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2422 
2423  /* Set the DMA error callback */
2424  hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2425 
2426  /* Set the unused DMA callbacks to NULL */
2427  hi2c->hdmarx->XferHalfCpltCallback = NULL;
2428  hi2c->hdmarx->XferM1CpltCallback = NULL;
2429  hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
2430  hi2c->hdmarx->XferAbortCallback = NULL;
2431 
2432  /* Enable the DMA stream */
2433  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2434  }
2435  else
2436  {
2437  /* Update I2C state */
2438  hi2c->State = HAL_I2C_STATE_LISTEN;
2439  hi2c->Mode = HAL_I2C_MODE_NONE;
2440 
2441  /* Update I2C error code */
2442  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2443 
2444  /* Process Unlocked */
2445  __HAL_UNLOCK(hi2c);
2446 
2447  return HAL_ERROR;
2448  }
2449 
2450  if (dmaxferstatus == HAL_OK)
2451  {
2452  /* Enable Address Acknowledge */
2453  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2454 
2455  /* Process Unlocked */
2456  __HAL_UNLOCK(hi2c);
2457 
2458  /* Note : The I2C interrupts must be enabled after unlocking current process
2459  to avoid the risk of I2C interrupt handle execution before current
2460  process unlock */
2461  /* Enable EVT and ERR interrupt */
2462  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2463 
2464  /* Enable DMA Request */
2465  SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2466 
2467  return HAL_OK;
2468  }
2469  else
2470  {
2471  /* Update I2C state */
2472  hi2c->State = HAL_I2C_STATE_READY;
2473  hi2c->Mode = HAL_I2C_MODE_NONE;
2474 
2475  /* Update I2C error code */
2476  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2477 
2478  /* Process Unlocked */
2479  __HAL_UNLOCK(hi2c);
2480 
2481  return HAL_ERROR;
2482  }
2483  }
2484  else
2485  {
2486  return HAL_BUSY;
2487  }
2488 }
2489 
2503 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2504 {
2505  /* Init tickstart for timeout management*/
2506  uint32_t tickstart = HAL_GetTick();
2507 
2508  /* Check the parameters */
2509  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2510 
2511  if (hi2c->State == HAL_I2C_STATE_READY)
2512  {
2513  /* Wait until BUSY flag is reset */
2514  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2515  {
2516  return HAL_BUSY;
2517  }
2518 
2519  /* Process Locked */
2520  __HAL_LOCK(hi2c);
2521 
2522  /* Check if the I2C is already enabled */
2523  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2524  {
2525  /* Enable I2C peripheral */
2526  __HAL_I2C_ENABLE(hi2c);
2527  }
2528 
2529  /* Disable Pos */
2530  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2531 
2532  hi2c->State = HAL_I2C_STATE_BUSY_TX;
2533  hi2c->Mode = HAL_I2C_MODE_MEM;
2534  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2535 
2536  /* Prepare transfer parameters */
2537  hi2c->pBuffPtr = pData;
2538  hi2c->XferCount = Size;
2539  hi2c->XferSize = hi2c->XferCount;
2540  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2541 
2542  /* Send Slave Address and Memory Address */
2543  if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2544  {
2545  return HAL_ERROR;
2546  }
2547 
2548  while (hi2c->XferSize > 0U)
2549  {
2550  /* Wait until TXE flag is set */
2551  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2552  {
2553  if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2554  {
2555  /* Generate Stop */
2556  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2557  }
2558  return HAL_ERROR;
2559  }
2560 
2561  /* Write data to DR */
2562  hi2c->Instance->DR = *hi2c->pBuffPtr;
2563 
2564  /* Increment Buffer pointer */
2565  hi2c->pBuffPtr++;
2566 
2567  /* Update counter */
2568  hi2c->XferSize--;
2569  hi2c->XferCount--;
2570 
2571  if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
2572  {
2573  /* Write data to DR */
2574  hi2c->Instance->DR = *hi2c->pBuffPtr;
2575 
2576  /* Increment Buffer pointer */
2577  hi2c->pBuffPtr++;
2578 
2579  /* Update counter */
2580  hi2c->XferSize--;
2581  hi2c->XferCount--;
2582  }
2583  }
2584 
2585  /* Wait until BTF flag is set */
2586  if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2587  {
2588  if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2589  {
2590  /* Generate Stop */
2591  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2592  }
2593  return HAL_ERROR;
2594  }
2595 
2596  /* Generate Stop */
2597  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2598 
2599  hi2c->State = HAL_I2C_STATE_READY;
2600  hi2c->Mode = HAL_I2C_MODE_NONE;
2601 
2602  /* Process Unlocked */
2603  __HAL_UNLOCK(hi2c);
2604 
2605  return HAL_OK;
2606  }
2607  else
2608  {
2609  return HAL_BUSY;
2610  }
2611 }
2612 
2626 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2627 {
2628  /* Init tickstart for timeout management*/
2629  uint32_t tickstart = HAL_GetTick();
2630 
2631  /* Check the parameters */
2632  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2633 
2634  if (hi2c->State == HAL_I2C_STATE_READY)
2635  {
2636  /* Wait until BUSY flag is reset */
2637  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2638  {
2639  return HAL_BUSY;
2640  }
2641 
2642  /* Process Locked */
2643  __HAL_LOCK(hi2c);
2644 
2645  /* Check if the I2C is already enabled */
2646  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2647  {
2648  /* Enable I2C peripheral */
2649  __HAL_I2C_ENABLE(hi2c);
2650  }
2651 
2652  /* Disable Pos */
2653  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2654 
2655  hi2c->State = HAL_I2C_STATE_BUSY_RX;
2656  hi2c->Mode = HAL_I2C_MODE_MEM;
2657  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2658 
2659  /* Prepare transfer parameters */
2660  hi2c->pBuffPtr = pData;
2661  hi2c->XferCount = Size;
2662  hi2c->XferSize = hi2c->XferCount;
2663  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2664 
2665  /* Send Slave Address and Memory Address */
2666  if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2667  {
2668  return HAL_ERROR;
2669  }
2670 
2671  if (hi2c->XferSize == 0U)
2672  {
2673  /* Clear ADDR flag */
2674  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2675 
2676  /* Generate Stop */
2677  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2678  }
2679  else if (hi2c->XferSize == 1U)
2680  {
2681  /* Disable Acknowledge */
2682  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2683 
2684  /* Clear ADDR flag */
2685  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2686 
2687  /* Generate Stop */
2688  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2689  }
2690  else if (hi2c->XferSize == 2U)
2691  {
2692  /* Disable Acknowledge */
2693  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2694 
2695  /* Enable Pos */
2696  SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2697 
2698  /* Clear ADDR flag */
2699  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2700  }
2701  else
2702  {
2703  /* Clear ADDR flag */
2704  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2705  }
2706 
2707  while (hi2c->XferSize > 0U)
2708  {
2709  if (hi2c->XferSize <= 3U)
2710  {
2711  /* One byte */
2712  if (hi2c->XferSize == 1U)
2713  {
2714  /* Wait until RXNE flag is set */
2715  if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2716  {
2717  return HAL_ERROR;
2718  }
2719 
2720  /* Read data from DR */
2721  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2722 
2723  /* Increment Buffer pointer */
2724  hi2c->pBuffPtr++;
2725 
2726  /* Update counter */
2727  hi2c->XferSize--;
2728  hi2c->XferCount--;
2729  }
2730  /* Two bytes */
2731  else if (hi2c->XferSize == 2U)
2732  {
2733  /* Wait until BTF flag is set */
2734  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2735  {
2736  return HAL_ERROR;
2737  }
2738 
2739  /* Generate Stop */
2740  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2741 
2742  /* Read data from DR */
2743  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2744 
2745  /* Increment Buffer pointer */
2746  hi2c->pBuffPtr++;
2747 
2748  /* Update counter */
2749  hi2c->XferSize--;
2750  hi2c->XferCount--;
2751 
2752  /* Read data from DR */
2753  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2754 
2755  /* Increment Buffer pointer */
2756  hi2c->pBuffPtr++;
2757 
2758  /* Update counter */
2759  hi2c->XferSize--;
2760  hi2c->XferCount--;
2761  }
2762  /* 3 Last bytes */
2763  else
2764  {
2765  /* Wait until BTF flag is set */
2766  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2767  {
2768  return HAL_ERROR;
2769  }
2770 
2771  /* Disable Acknowledge */
2772  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2773 
2774  /* Read data from DR */
2775  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2776 
2777  /* Increment Buffer pointer */
2778  hi2c->pBuffPtr++;
2779 
2780  /* Update counter */
2781  hi2c->XferSize--;
2782  hi2c->XferCount--;
2783 
2784  /* Wait until BTF flag is set */
2785  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2786  {
2787  return HAL_ERROR;
2788  }
2789 
2790  /* Generate Stop */
2791  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2792 
2793  /* Read data from DR */
2794  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2795 
2796  /* Increment Buffer pointer */
2797  hi2c->pBuffPtr++;
2798 
2799  /* Update counter */
2800  hi2c->XferSize--;
2801  hi2c->XferCount--;
2802 
2803  /* Read data from DR */
2804  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2805 
2806  /* Increment Buffer pointer */
2807  hi2c->pBuffPtr++;
2808 
2809  /* Update counter */
2810  hi2c->XferSize--;
2811  hi2c->XferCount--;
2812  }
2813  }
2814  else
2815  {
2816  /* Wait until RXNE flag is set */
2817  if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2818  {
2819  return HAL_ERROR;
2820  }
2821 
2822  /* Read data from DR */
2823  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2824 
2825  /* Increment Buffer pointer */
2826  hi2c->pBuffPtr++;
2827 
2828  /* Update counter */
2829  hi2c->XferSize--;
2830  hi2c->XferCount--;
2831 
2832  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
2833  {
2834  if (hi2c->XferSize == 3U)
2835  {
2836  /* Disable Acknowledge */
2837  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2838  }
2839  /* Read data from DR */
2840  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2841 
2842  /* Increment Buffer pointer */
2843  hi2c->pBuffPtr++;
2844 
2845  /* Update counter */
2846  hi2c->XferSize--;
2847  hi2c->XferCount--;
2848  }
2849  }
2850  }
2851 
2852  hi2c->State = HAL_I2C_STATE_READY;
2853  hi2c->Mode = HAL_I2C_MODE_NONE;
2854 
2855  /* Process Unlocked */
2856  __HAL_UNLOCK(hi2c);
2857 
2858  return HAL_OK;
2859  }
2860  else
2861  {
2862  return HAL_BUSY;
2863  }
2864 }
2865 
2878 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2879 {
2880  __IO uint32_t count = 0U;
2881 
2882  /* Check the parameters */
2883  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2884 
2885  if (hi2c->State == HAL_I2C_STATE_READY)
2886  {
2887  /* Wait until BUSY flag is reset */
2888  count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2889  do
2890  {
2891  count--;
2892  if (count == 0U)
2893  {
2894  hi2c->PreviousState = I2C_STATE_NONE;
2895  hi2c->State = HAL_I2C_STATE_READY;
2896  hi2c->Mode = HAL_I2C_MODE_NONE;
2897  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2898 
2899  return HAL_BUSY;
2900  }
2901  }
2902  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2903 
2904  /* Process Locked */
2905  __HAL_LOCK(hi2c);
2906 
2907  /* Check if the I2C is already enabled */
2908  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2909  {
2910  /* Enable I2C peripheral */
2911  __HAL_I2C_ENABLE(hi2c);
2912  }
2913 
2914  /* Disable Pos */
2915  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2916 
2917  hi2c->State = HAL_I2C_STATE_BUSY_TX;
2918  hi2c->Mode = HAL_I2C_MODE_MEM;
2919  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2920 
2921  /* Prepare transfer parameters */
2922  hi2c->pBuffPtr = pData;
2923  hi2c->XferCount = Size;
2924  hi2c->XferSize = hi2c->XferCount;
2925  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2926  hi2c->Devaddress = DevAddress;
2927  hi2c->Memaddress = MemAddress;
2928  hi2c->MemaddSize = MemAddSize;
2929  hi2c->EventCount = 0U;
2930 
2931  /* Generate Start */
2932  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2933 
2934  /* Process Unlocked */
2935  __HAL_UNLOCK(hi2c);
2936 
2937  /* Note : The I2C interrupts must be enabled after unlocking current process
2938  to avoid the risk of I2C interrupt handle execution before current
2939  process unlock */
2940 
2941  /* Enable EVT, BUF and ERR interrupt */
2942  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2943 
2944  return HAL_OK;
2945  }
2946  else
2947  {
2948  return HAL_BUSY;
2949  }
2950 }
2951 
2963 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2964 {
2965  __IO uint32_t count = 0U;
2966 
2967  /* Check the parameters */
2968  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2969 
2970  if (hi2c->State == HAL_I2C_STATE_READY)
2971  {
2972  /* Wait until BUSY flag is reset */
2973  count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2974  do
2975  {
2976  count--;
2977  if (count == 0U)
2978  {
2979  hi2c->PreviousState = I2C_STATE_NONE;
2980  hi2c->State = HAL_I2C_STATE_READY;
2981  hi2c->Mode = HAL_I2C_MODE_NONE;
2982  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2983 
2984  return HAL_BUSY;
2985  }
2986  }
2987  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2988 
2989  /* Process Locked */
2990  __HAL_LOCK(hi2c);
2991 
2992  /* Check if the I2C is already enabled */
2993  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2994  {
2995  /* Enable I2C peripheral */
2996  __HAL_I2C_ENABLE(hi2c);
2997  }
2998 
2999  /* Disable Pos */
3000  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3001 
3002  hi2c->State = HAL_I2C_STATE_BUSY_RX;
3003  hi2c->Mode = HAL_I2C_MODE_MEM;
3004  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3005 
3006  /* Prepare transfer parameters */
3007  hi2c->pBuffPtr = pData;
3008  hi2c->XferCount = Size;
3009  hi2c->XferSize = hi2c->XferCount;
3010  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3011  hi2c->Devaddress = DevAddress;
3012  hi2c->Memaddress = MemAddress;
3013  hi2c->MemaddSize = MemAddSize;
3014  hi2c->EventCount = 0U;
3015 
3016  /* Enable Acknowledge */
3017  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3018 
3019  /* Generate Start */
3020  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3021 
3022  /* Process Unlocked */
3023  __HAL_UNLOCK(hi2c);
3024 
3025  if (hi2c->XferSize > 0U)
3026  {
3027  /* Note : The I2C interrupts must be enabled after unlocking current process
3028  to avoid the risk of I2C interrupt handle execution before current
3029  process unlock */
3030 
3031  /* Enable EVT, BUF and ERR interrupt */
3032  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3033  }
3034  return HAL_OK;
3035  }
3036  else
3037  {
3038  return HAL_BUSY;
3039  }
3040 }
3041 
3054 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3055 {
3056  __IO uint32_t count = 0U;
3057  HAL_StatusTypeDef dmaxferstatus;
3058 
3059  /* Init tickstart for timeout management*/
3060  uint32_t tickstart = HAL_GetTick();
3061 
3062  /* Check the parameters */
3063  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3064 
3065  if (hi2c->State == HAL_I2C_STATE_READY)
3066  {
3067  /* Wait until BUSY flag is reset */
3068  count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3069  do
3070  {
3071  count--;
3072  if (count == 0U)
3073  {
3074  hi2c->PreviousState = I2C_STATE_NONE;
3075  hi2c->State = HAL_I2C_STATE_READY;
3076  hi2c->Mode = HAL_I2C_MODE_NONE;
3077  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3078 
3079  return HAL_BUSY;
3080  }
3081  }
3082  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3083 
3084  /* Process Locked */
3085  __HAL_LOCK(hi2c);
3086 
3087  /* Check if the I2C is already enabled */
3088  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3089  {
3090  /* Enable I2C peripheral */
3091  __HAL_I2C_ENABLE(hi2c);
3092  }
3093 
3094  /* Disable Pos */
3095  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3096 
3097  hi2c->State = HAL_I2C_STATE_BUSY_TX;
3098  hi2c->Mode = HAL_I2C_MODE_MEM;
3099  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3100 
3101  /* Prepare transfer parameters */
3102  hi2c->pBuffPtr = pData;
3103  hi2c->XferCount = Size;
3104  hi2c->XferSize = hi2c->XferCount;
3105  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3106  hi2c->Devaddress = DevAddress;
3107  hi2c->Memaddress = MemAddress;
3108  hi2c->MemaddSize = MemAddSize;
3109  hi2c->EventCount = 0U;
3110 
3111  if (hi2c->XferSize > 0U)
3112  {
3113  if (hi2c->hdmatx != NULL)
3114  {
3115  /* Set the I2C DMA transfer complete callback */
3116  hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3117 
3118  /* Set the DMA error callback */
3119  hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3120 
3121  /* Set the unused DMA callbacks to NULL */
3122  hi2c->hdmatx->XferHalfCpltCallback = NULL;
3123  hi2c->hdmatx->XferM1CpltCallback = NULL;
3124  hi2c->hdmatx->XferM1HalfCpltCallback = NULL;
3125  hi2c->hdmatx->XferAbortCallback = NULL;
3126 
3127  /* Enable the DMA stream */
3128  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3129  }
3130  else
3131  {
3132  /* Update I2C state */
3133  hi2c->State = HAL_I2C_STATE_READY;
3134  hi2c->Mode = HAL_I2C_MODE_NONE;
3135 
3136  /* Update I2C error code */
3137  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3138 
3139  /* Process Unlocked */
3140  __HAL_UNLOCK(hi2c);
3141 
3142  return HAL_ERROR;
3143  }
3144 
3145  if (dmaxferstatus == HAL_OK)
3146  {
3147  /* Send Slave Address and Memory Address */
3148  if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3149  {
3150  /* Abort the ongoing DMA */
3151  dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx);
3152 
3153  /* Prevent unused argument(s) compilation and MISRA warning */
3154  UNUSED(dmaxferstatus);
3155 
3156  /* Set the unused I2C DMA transfer complete callback to NULL */
3157  hi2c->hdmatx->XferCpltCallback = NULL;
3158 
3159  /* Disable Acknowledge */
3160  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3161 
3162  hi2c->XferSize = 0U;
3163  hi2c->XferCount = 0U;
3164 
3165  /* Disable I2C peripheral to prevent dummy data in buffer */
3166  __HAL_I2C_DISABLE(hi2c);
3167 
3168  return HAL_ERROR;
3169  }
3170 
3171  /* Clear ADDR flag */
3172  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3173 
3174  /* Process Unlocked */
3175  __HAL_UNLOCK(hi2c);
3176 
3177  /* Note : The I2C interrupts must be enabled after unlocking current process
3178  to avoid the risk of I2C interrupt handle execution before current
3179  process unlock */
3180  /* Enable ERR interrupt */
3181  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3182 
3183  /* Enable DMA Request */
3184  SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3185 
3186  return HAL_OK;
3187  }
3188  else
3189  {
3190  /* Update I2C state */
3191  hi2c->State = HAL_I2C_STATE_READY;
3192  hi2c->Mode = HAL_I2C_MODE_NONE;
3193 
3194  /* Update I2C error code */
3195  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3196 
3197  /* Process Unlocked */
3198  __HAL_UNLOCK(hi2c);
3199 
3200  return HAL_ERROR;
3201  }
3202  }
3203  else
3204  {
3205  /* Update I2C state */
3206  hi2c->State = HAL_I2C_STATE_READY;
3207  hi2c->Mode = HAL_I2C_MODE_NONE;
3208 
3209  /* Update I2C error code */
3210  hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
3211 
3212  /* Process Unlocked */
3213  __HAL_UNLOCK(hi2c);
3214 
3215  return HAL_ERROR;
3216  }
3217  }
3218  else
3219  {
3220  return HAL_BUSY;
3221  }
3222 }
3223 
3236 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3237 {
3238  /* Init tickstart for timeout management*/
3239  uint32_t tickstart = HAL_GetTick();
3240  __IO uint32_t count = 0U;
3241  HAL_StatusTypeDef dmaxferstatus;
3242 
3243  /* Check the parameters */
3244  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3245 
3246  if (hi2c->State == HAL_I2C_STATE_READY)
3247  {
3248  /* Wait until BUSY flag is reset */
3249  count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3250  do
3251  {
3252  count--;
3253  if (count == 0U)
3254  {
3255  hi2c->PreviousState = I2C_STATE_NONE;
3256  hi2c->State = HAL_I2C_STATE_READY;
3257  hi2c->Mode = HAL_I2C_MODE_NONE;
3258  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3259 
3260  return HAL_BUSY;
3261  }
3262  }
3263  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3264 
3265  /* Process Locked */
3266  __HAL_LOCK(hi2c);
3267 
3268  /* Check if the I2C is already enabled */
3269  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3270  {
3271  /* Enable I2C peripheral */
3272  __HAL_I2C_ENABLE(hi2c);
3273  }
3274 
3275  /* Disable Pos */
3276  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3277 
3278  hi2c->State = HAL_I2C_STATE_BUSY_RX;
3279  hi2c->Mode = HAL_I2C_MODE_MEM;
3280  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3281 
3282  /* Prepare transfer parameters */
3283  hi2c->pBuffPtr = pData;
3284  hi2c->XferCount = Size;
3285  hi2c->XferSize = hi2c->XferCount;
3286  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3287  hi2c->Devaddress = DevAddress;
3288  hi2c->Memaddress = MemAddress;
3289  hi2c->MemaddSize = MemAddSize;
3290  hi2c->EventCount = 0U;
3291 
3292  if (hi2c->XferSize > 0U)
3293  {
3294  if (hi2c->hdmarx != NULL)
3295  {
3296  /* Set the I2C DMA transfer complete callback */
3297  hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
3298 
3299  /* Set the DMA error callback */
3300  hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3301 
3302  /* Set the unused DMA callbacks to NULL */
3303  hi2c->hdmarx->XferHalfCpltCallback = NULL;
3304  hi2c->hdmarx->XferM1CpltCallback = NULL;
3305  hi2c->hdmarx->XferM1HalfCpltCallback = NULL;
3306  hi2c->hdmarx->XferAbortCallback = NULL;
3307 
3308  /* Enable the DMA stream */
3309  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
3310  }
3311  else
3312  {
3313  /* Update I2C state */
3314  hi2c->State = HAL_I2C_STATE_READY;
3315  hi2c->Mode = HAL_I2C_MODE_NONE;
3316 
3317  /* Update I2C error code */
3318  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3319 
3320  /* Process Unlocked */
3321  __HAL_UNLOCK(hi2c);
3322 
3323  return HAL_ERROR;
3324  }
3325 
3326  if (dmaxferstatus == HAL_OK)
3327  {
3328  /* Send Slave Address and Memory Address */
3329  if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3330  {
3331  /* Abort the ongoing DMA */
3332  dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx);
3333 
3334  /* Prevent unused argument(s) compilation and MISRA warning */
3335  UNUSED(dmaxferstatus);
3336 
3337  /* Set the unused I2C DMA transfer complete callback to NULL */
3338  hi2c->hdmarx->XferCpltCallback = NULL;
3339 
3340  /* Disable Acknowledge */
3341  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3342 
3343  hi2c->XferSize = 0U;
3344  hi2c->XferCount = 0U;
3345 
3346  /* Disable I2C peripheral to prevent dummy data in buffer */
3347  __HAL_I2C_DISABLE(hi2c);
3348 
3349  return HAL_ERROR;
3350  }
3351 
3352  if (hi2c->XferSize == 1U)
3353  {
3354  /* Disable Acknowledge */
3355  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3356  }
3357  else
3358  {
3359  /* Enable Last DMA bit */
3360  SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
3361  }
3362 
3363  /* Clear ADDR flag */
3364  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3365 
3366  /* Process Unlocked */
3367  __HAL_UNLOCK(hi2c);
3368 
3369  /* Note : The I2C interrupts must be enabled after unlocking current process
3370  to avoid the risk of I2C interrupt handle execution before current
3371  process unlock */
3372  /* Enable ERR interrupt */
3373  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3374 
3375  /* Enable DMA Request */
3376  hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
3377  }
3378  else
3379  {
3380  /* Update I2C state */
3381  hi2c->State = HAL_I2C_STATE_READY;
3382  hi2c->Mode = HAL_I2C_MODE_NONE;
3383 
3384  /* Update I2C error code */
3385  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3386 
3387  /* Process Unlocked */
3388  __HAL_UNLOCK(hi2c);
3389 
3390  return HAL_ERROR;
3391  }
3392  }
3393  else
3394  {
3395  /* Send Slave Address and Memory Address */
3396  if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3397  {
3398  return HAL_ERROR;
3399  }
3400 
3401  /* Clear ADDR flag */
3402  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3403 
3404  /* Generate Stop */
3405  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3406 
3407  hi2c->State = HAL_I2C_STATE_READY;
3408 
3409  /* Process Unlocked */
3410  __HAL_UNLOCK(hi2c);
3411  }
3412 
3413  return HAL_OK;
3414  }
3415  else
3416  {
3417  return HAL_BUSY;
3418  }
3419 }
3420 
3432 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
3433 {
3434  /* Get tick */
3435  uint32_t tickstart = HAL_GetTick();
3436  uint32_t I2C_Trials = 0U;
3437  FlagStatus tmp1;
3438  FlagStatus tmp2;
3439 
3440  if (hi2c->State == HAL_I2C_STATE_READY)
3441  {
3442  /* Wait until BUSY flag is reset */
3443  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3444  {
3445  return HAL_BUSY;
3446  }
3447 
3448  /* Process Locked */
3449  __HAL_LOCK(hi2c);
3450 
3451  /* Check if the I2C is already enabled */
3452  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3453  {
3454  /* Enable I2C peripheral */
3455  __HAL_I2C_ENABLE(hi2c);
3456  }
3457 
3458  /* Disable Pos */
3459  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3460 
3461  hi2c->State = HAL_I2C_STATE_BUSY;
3462  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3463  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3464 
3465  do
3466  {
3467  /* Generate Start */
3468  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3469 
3470  /* Wait until SB flag is set */
3471  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
3472  {
3473  if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
3474  {
3475  hi2c->ErrorCode = HAL_I2C_WRONG_START;
3476  }
3477  return HAL_TIMEOUT;
3478  }
3479 
3480  /* Send slave address */
3481  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
3482 
3483  /* Wait until ADDR or AF flag are set */
3484  /* Get tick */
3485  tickstart = HAL_GetTick();
3486 
3487  tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3488  tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3489  while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET))
3490  {
3491  if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3492  {
3493  hi2c->State = HAL_I2C_STATE_TIMEOUT;
3494  }
3495  tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3496  tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3497  }
3498 
3499  hi2c->State = HAL_I2C_STATE_READY;
3500 
3501  /* Check if the ADDR flag has been set */
3502  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
3503  {
3504  /* Generate Stop */
3505  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3506 
3507  /* Clear ADDR Flag */
3508  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3509 
3510  /* Wait until BUSY flag is reset */
3511  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3512  {
3513  return HAL_ERROR;
3514  }
3515 
3516  hi2c->State = HAL_I2C_STATE_READY;
3517 
3518  /* Process Unlocked */
3519  __HAL_UNLOCK(hi2c);
3520 
3521  return HAL_OK;
3522  }
3523  else
3524  {
3525  /* Generate Stop */
3526  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3527 
3528  /* Clear AF Flag */
3529  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3530 
3531  /* Wait until BUSY flag is reset */
3532  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3533  {
3534  return HAL_ERROR;
3535  }
3536  }
3537 
3538  /* Increment Trials */
3539  I2C_Trials++;
3540  }
3541  while (I2C_Trials < Trials);
3542 
3543  hi2c->State = HAL_I2C_STATE_READY;
3544 
3545  /* Process Unlocked */
3546  __HAL_UNLOCK(hi2c);
3547 
3548  return HAL_ERROR;
3549  }
3550  else
3551  {
3552  return HAL_BUSY;
3553  }
3554 }
3555 
3568 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3569 {
3570  __IO uint32_t Prev_State = 0x00U;
3571  __IO uint32_t count = 0x00U;
3572 
3573  /* Check the parameters */
3574  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3575 
3576  if (hi2c->State == HAL_I2C_STATE_READY)
3577  {
3578  /* Check Busy Flag only if FIRST call of Master interface */
3579  if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3580  {
3581  /* Wait until BUSY flag is reset */
3582  count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3583  do
3584  {
3585  count--;
3586  if (count == 0U)
3587  {
3588  hi2c->PreviousState = I2C_STATE_NONE;
3589  hi2c->State = HAL_I2C_STATE_READY;
3590  hi2c->Mode = HAL_I2C_MODE_NONE;
3591  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3592 
3593  return HAL_BUSY;
3594  }
3595  }
3596  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3597  }
3598 
3599  /* Process Locked */
3600  __HAL_LOCK(hi2c);
3601 
3602  /* Check if the I2C is already enabled */
3603  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3604  {
3605  /* Enable I2C peripheral */
3606  __HAL_I2C_ENABLE(hi2c);
3607  }
3608 
3609  /* Disable Pos */
3610  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3611 
3612  hi2c->State = HAL_I2C_STATE_BUSY_TX;
3613  hi2c->Mode = HAL_I2C_MODE_MASTER;
3614  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3615 
3616  /* Prepare transfer parameters */
3617  hi2c->pBuffPtr = pData;
3618  hi2c->XferCount = Size;
3619  hi2c->XferSize = hi2c->XferCount;
3620  hi2c->XferOptions = XferOptions;
3621  hi2c->Devaddress = DevAddress;
3622 
3623  Prev_State = hi2c->PreviousState;
3624 
3625  /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3626  /* Mean Previous state is same as current state */
3627  if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3628  {
3629  /* Generate Start */
3630  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3631  }
3632 
3633  /* Process Unlocked */
3634  __HAL_UNLOCK(hi2c);
3635 
3636  /* Note : The I2C interrupts must be enabled after unlocking current process
3637  to avoid the risk of I2C interrupt handle execution before current
3638  process unlock */
3639 
3640  /* Enable EVT, BUF and ERR interrupt */
3641  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3642 
3643  return HAL_OK;
3644  }
3645  else
3646  {
3647  return HAL_BUSY;
3648  }
3649 }
3650 
3663 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3664 {
3665  __IO uint32_t Prev_State = 0x00U;
3666  __IO uint32_t count = 0x00U;
3667  HAL_StatusTypeDef dmaxferstatus;
3668 
3669  /* Check the parameters */
3670  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3671 
3672  if (hi2c->State == HAL_I2C_STATE_READY)
3673  {
3674  /* Check Busy Flag only if FIRST call of Master interface */
3675  if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3676  {
3677  /* Wait until BUSY flag is reset */
3678  count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3679  do
3680  {
3681  count--;
3682  if (count == 0U)
3683  {
3684  hi2c->PreviousState = I2C_STATE_NONE;
3685  hi2c->State = HAL_I2C_STATE_READY;
3686  hi2c->Mode = HAL_I2C_MODE_NONE;
3687  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3688 
3689  return HAL_BUSY;
3690  }
3691  }
3692  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3693  }
3694 
3695  /* Process Locked */
3696  __HAL_LOCK(hi2c);
3697 
3698  /* Check if the I2C is already enabled */
3699  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3700  {
3701  /* Enable I2C peripheral */
3702  __HAL_I2C_ENABLE(hi2c);
3703  }
3704 
3705  /* Disable Pos */
3706  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3707 
3708  hi2c->State = HAL_I2C_STATE_BUSY_TX;
3709  hi2c->Mode = HAL_I2C_MODE_MASTER;
3710  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3711 
3712  /* Prepare transfer parameters */
3713  hi2c->pBuffPtr = pData;
3714  hi2c->XferCount = Size;
3715  hi2c->XferSize = hi2c->XferCount;
3716  hi2c->XferOptions = XferOptions;
3717  hi2c->Devaddress = DevAddress;
3718 
3719  Prev_State = hi2c->PreviousState;
3720 
3721  if (hi2c->XferSize > 0U)
3722  {
3723  if (hi2c->hdmatx != NULL)
3724  {
3725  /* Set the I2C DMA transfer complete callback */
3726  hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3727 
3728  /* Set the DMA error callback */
3729  hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3730 
3731  /* Set the unused DMA callbacks to NULL */
3732  hi2c->hdmatx->XferHalfCpltCallback = NULL;
3733  hi2c->hdmatx->XferAbortCallback = NULL;
3734 
3735  /* Enable the DMA stream */
3736  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3737  }
3738  else
3739  {
3740  /* Update I2C state */
3741  hi2c->State = HAL_I2C_STATE_READY;
3742  hi2c->Mode = HAL_I2C_MODE_NONE;
3743 
3744  /* Update I2C error code */
3745  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3746 
3747  /* Process Unlocked */
3748  __HAL_UNLOCK(hi2c);
3749 
3750  return HAL_ERROR;
3751  }
3752 
3753  if (dmaxferstatus == HAL_OK)
3754  {
3755  /* Enable Acknowledge */
3756  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3757 
3758  /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3759  /* Mean Previous state is same as current state */
3760  if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3761  {
3762  /* Generate Start */
3763  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3764  }
3765 
3766  /* Process Unlocked */
3767  __HAL_UNLOCK(hi2c);
3768 
3769  /* Note : The I2C interrupts must be enabled after unlocking current process
3770  to avoid the risk of I2C interrupt handle execution before current
3771  process unlock */
3772 
3773  /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
3774  /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
3775  if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
3776  {
3777  /* Enable DMA Request */
3778  SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3779  }
3780 
3781  /* Enable EVT and ERR interrupt */
3782  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
3783  }
3784  else
3785  {
3786  /* Update I2C state */
3787  hi2c->State = HAL_I2C_STATE_READY;
3788  hi2c->Mode = HAL_I2C_MODE_NONE;
3789 
3790  /* Update I2C error code */
3791  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3792 
3793  /* Process Unlocked */
3794  __HAL_UNLOCK(hi2c);
3795 
3796  return HAL_ERROR;
3797  }
3798  }
3799  else
3800  {
3801  /* Enable Acknowledge */
3802  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3803 
3804  /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3805  /* Mean Previous state is same as current state */
3806  if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3807  {
3808  /* Generate Start */
3809  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3810  }
3811 
3812  /* Process Unlocked */
3813  __HAL_UNLOCK(hi2c);
3814 
3815  /* Note : The I2C interrupts must be enabled after unlocking current process
3816  to avoid the risk of I2C interrupt handle execution before current
3817  process unlock */
3818 
3819  /* Enable EVT, BUF and ERR interrupt */
3820  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3821  }
3822 
3823  return HAL_OK;
3824  }
3825  else
3826  {
3827  return HAL_BUSY;
3828  }
3829 }
3830 
3843 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3844 {
3845  __IO uint32_t Prev_State = 0x00U;
3846  __IO uint32_t count = 0U;
3847  uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3848 
3849  /* Check the parameters */
3850  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3851 
3852  if (hi2c->State == HAL_I2C_STATE_READY)
3853  {
3854  /* Check Busy Flag only if FIRST call of Master interface */
3855  if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3856  {
3857  /* Wait until BUSY flag is reset */
3858  count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3859  do
3860  {
3861  count--;
3862  if (count == 0U)
3863  {
3864  hi2c->PreviousState = I2C_STATE_NONE;
3865  hi2c->State = HAL_I2C_STATE_READY;
3866  hi2c->Mode = HAL_I2C_MODE_NONE;
3867  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3868 
3869  return HAL_BUSY;
3870  }
3871  }
3872  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3873  }
3874 
3875  /* Process Locked */
3876  __HAL_LOCK(hi2c);
3877 
3878  /* Check if the I2C is already enabled */
3879  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3880  {
3881  /* Enable I2C peripheral */
3882  __HAL_I2C_ENABLE(hi2c);
3883  }
3884 
3885  /* Disable Pos */
3886  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3887 
3888  hi2c->State = HAL_I2C_STATE_BUSY_RX;
3889  hi2c->Mode = HAL_I2C_MODE_MASTER;
3890  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3891 
3892  /* Prepare transfer parameters */
3893  hi2c->pBuffPtr = pData;
3894  hi2c->XferCount = Size;
3895  hi2c->XferSize = hi2c->XferCount;
3896  hi2c->XferOptions = XferOptions;
3897  hi2c->Devaddress = DevAddress;
3898 
3899  Prev_State = hi2c->PreviousState;
3900 
3901  if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
3902  {
3903  if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
3904  {
3905  /* Disable Acknowledge */
3906  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3907 
3908  /* Enable Pos */
3909  SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3910 
3911  /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */
3912  enableIT &= ~I2C_IT_BUF;
3913  }
3914  else
3915  {
3916  /* Enable Acknowledge */
3917  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3918  }
3919  }
3920  else
3921  {
3922  /* Enable Acknowledge */
3923  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3924  }
3925 
3926  /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3927  /* Mean Previous state is same as current state */
3928  if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3929  {
3930  /* Generate Start */
3931  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3932  }
3933 
3934  /* Process Unlocked */
3935  __HAL_UNLOCK(hi2c);
3936 
3937  /* Note : The I2C interrupts must be enabled after unlocking current process
3938  to avoid the risk of I2C interrupt handle execution before current
3939  process unlock */
3940 
3941  /* Enable interrupts */
3942  __HAL_I2C_ENABLE_IT(hi2c, enableIT);
3943 
3944  return HAL_OK;
3945  }
3946  else
3947  {
3948  return HAL_BUSY;
3949  }
3950 }
3951 
3964 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3965 {
3966  __IO uint32_t Prev_State = 0x00U;
3967  __IO uint32_t count = 0U;
3968  uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3969  HAL_StatusTypeDef dmaxferstatus;
3970 
3971  /* Check the parameters */
3972  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3973 
3974  if (hi2c->State == HAL_I2C_STATE_READY)
3975  {
3976  /* Check Busy Flag only if FIRST call of Master interface */
3977  if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3978  {
3979  /* Wait until BUSY flag is reset */
3980  count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3981  do
3982  {
3983  count--;
3984  if (count == 0U)
3985  {
3986  hi2c->PreviousState = I2C_STATE_NONE;
3987  hi2c->State = HAL_I2C_STATE_READY;
3988  hi2c->Mode = HAL_I2C_MODE_NONE;
3989  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3990 
3991  return HAL_BUSY;
3992  }
3993  }
3994  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3995  }
3996 
3997  /* Process Locked */
3998  __HAL_LOCK(hi2c);
3999 
4000  /* Check if the I2C is already enabled */
4001  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4002  {
4003  /* Enable I2C peripheral */
4004  __HAL_I2C_ENABLE(hi2c);
4005  }
4006 
4007  /* Disable Pos */
4008  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4009 
4010  /* Clear Last DMA bit */
4011  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4012 
4013  hi2c->State = HAL_I2C_STATE_BUSY_RX;
4014  hi2c->Mode = HAL_I2C_MODE_MASTER;
4015  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4016 
4017  /* Prepare transfer parameters */
4018  hi2c->pBuffPtr = pData;
4019  hi2c->XferCount = Size;
4020  hi2c->XferSize = hi2c->XferCount;
4021  hi2c->XferOptions = XferOptions;
4022  hi2c->Devaddress = DevAddress;
4023 
4024  Prev_State = hi2c->PreviousState;
4025 
4026  if (hi2c->XferSize > 0U)
4027  {
4028  if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
4029  {
4030  if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
4031  {
4032  /* Disable Acknowledge */
4033  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4034 
4035  /* Enable Pos */
4036  SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4037 
4038  /* Enable Last DMA bit */
4039  SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4040  }
4041  else
4042  {
4043  /* Enable Acknowledge */
4044  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4045  }
4046  }
4047  else
4048  {
4049  /* Enable Acknowledge */
4050  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4051 
4052  if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
4053  {
4054  /* Enable Last DMA bit */
4055  SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4056  }
4057  }
4058  if (hi2c->hdmarx != NULL)
4059  {
4060  /* Set the I2C DMA transfer complete callback */
4061  hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
4062 
4063  /* Set the DMA error callback */
4064  hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4065 
4066  /* Set the unused DMA callbacks to NULL */
4067  hi2c->hdmarx->XferHalfCpltCallback = NULL;
4068  hi2c->hdmarx->XferAbortCallback = NULL;
4069 
4070  /* Enable the DMA stream */
4071  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
4072  }
4073  else
4074  {
4075  /* Update I2C state */
4076  hi2c->State = HAL_I2C_STATE_READY;
4077  hi2c->Mode = HAL_I2C_MODE_NONE;
4078 
4079  /* Update I2C error code */
4080  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4081 
4082  /* Process Unlocked */
4083  __HAL_UNLOCK(hi2c);
4084 
4085  return HAL_ERROR;
4086  }
4087  if (dmaxferstatus == HAL_OK)
4088  {
4089  /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
4090  /* Mean Previous state is same as current state */
4091  if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
4092  {
4093  /* Generate Start */
4094  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4095 
4096  /* Update interrupt for only EVT and ERR */
4097  enableIT = (I2C_IT_EVT | I2C_IT_ERR);
4098  }
4099  else
4100  {
4101  /* Update interrupt for only ERR */
4102  enableIT = I2C_IT_ERR;
4103  }
4104 
4105  /* Process Unlocked */
4106  __HAL_UNLOCK(hi2c);
4107 
4108  /* Note : The I2C interrupts must be enabled after unlocking current process
4109  to avoid the risk of I2C interrupt handle execution before current
4110  process unlock */
4111 
4112  /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
4113  /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
4114  if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
4115  {
4116  /* Enable DMA Request */
4117  SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4118  }
4119 
4120  /* Enable EVT and ERR interrupt */
4121  __HAL_I2C_ENABLE_IT(hi2c, enableIT);
4122  }
4123  else
4124  {
4125  /* Update I2C state */
4126  hi2c->State = HAL_I2C_STATE_READY;
4127  hi2c->Mode = HAL_I2C_MODE_NONE;
4128 
4129  /* Update I2C error code */
4130  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4131 
4132  /* Process Unlocked */
4133  __HAL_UNLOCK(hi2c);
4134 
4135  return HAL_ERROR;
4136  }
4137  }
4138  else
4139  {
4140  /* Enable Acknowledge */
4141  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4142 
4143  /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
4144  /* Mean Previous state is same as current state */
4145  if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
4146  {
4147  /* Generate Start */
4148  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4149  }
4150 
4151  /* Process Unlocked */
4152  __HAL_UNLOCK(hi2c);
4153 
4154  /* Note : The I2C interrupts must be enabled after unlocking current process
4155  to avoid the risk of I2C interrupt handle execution before current
4156  process unlock */
4157 
4158  /* Enable interrupts */
4159  __HAL_I2C_ENABLE_IT(hi2c, enableIT);
4160  }
4161  return HAL_OK;
4162  }
4163  else
4164  {
4165  return HAL_BUSY;
4166  }
4167 }
4168 
4179 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4180 {
4181  /* Check the parameters */
4182  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4183 
4184  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4185  {
4186  if ((pData == NULL) || (Size == 0U))
4187  {
4188  return HAL_ERROR;
4189  }
4190 
4191  /* Process Locked */
4192  __HAL_LOCK(hi2c);
4193 
4194  /* Check if the I2C is already enabled */
4195  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4196  {
4197  /* Enable I2C peripheral */
4198  __HAL_I2C_ENABLE(hi2c);
4199  }
4200 
4201  /* Disable Pos */
4202  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4203 
4204  hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4205  hi2c->Mode = HAL_I2C_MODE_SLAVE;
4206  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4207 
4208  /* Prepare transfer parameters */
4209  hi2c->pBuffPtr = pData;
4210  hi2c->XferCount = Size;
4211  hi2c->XferSize = hi2c->XferCount;
4212  hi2c->XferOptions = XferOptions;
4213 
4214  /* Clear ADDR flag */
4215  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4216 
4217  /* Process Unlocked */
4218  __HAL_UNLOCK(hi2c);
4219 
4220  /* Note : The I2C interrupts must be enabled after unlocking current process
4221  to avoid the risk of I2C interrupt handle execution before current
4222  process unlock */
4223 
4224  /* Enable EVT, BUF and ERR interrupt */
4225  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4226 
4227  return HAL_OK;
4228  }
4229  else
4230  {
4231  return HAL_BUSY;
4232  }
4233 }
4234 
4245 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4246 {
4247  HAL_StatusTypeDef dmaxferstatus;
4248 
4249  /* Check the parameters */
4250  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4251 
4252  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4253  {
4254  if ((pData == NULL) || (Size == 0U))
4255  {
4256  return HAL_ERROR;
4257  }
4258 
4259  /* Process Locked */
4260  __HAL_LOCK(hi2c);
4261 
4262  /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4263  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4264 
4265  /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4266  /* and then toggle the HAL slave RX state to TX state */
4267  if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4268  {
4269  if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4270  {
4271  /* Abort DMA Xfer if any */
4272  if (hi2c->hdmarx != NULL)
4273  {
4274  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4275 
4276  /* Set the I2C DMA Abort callback :
4277  will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4278  hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4279 
4280  /* Abort DMA RX */
4281  if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4282  {
4283  /* Call Directly XferAbortCallback function in case of error */
4284  hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4285  }
4286  }
4287  }
4288  }
4289  else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4290  {
4291  if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4292  {
4293  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4294 
4295  /* Abort DMA Xfer if any */
4296  if (hi2c->hdmatx != NULL)
4297  {
4298  /* Set the I2C DMA Abort callback :
4299  will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4300  hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4301 
4302  /* Abort DMA TX */
4303  if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4304  {
4305  /* Call Directly XferAbortCallback function in case of error */
4306  hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4307  }
4308  }
4309  }
4310  }
4311  else
4312  {
4313  /* Nothing to do */
4314  }
4315 
4316  /* Check if the I2C is already enabled */
4317  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4318  {
4319  /* Enable I2C peripheral */
4320  __HAL_I2C_ENABLE(hi2c);
4321  }
4322 
4323  /* Disable Pos */
4324  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4325 
4326  hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4327  hi2c->Mode = HAL_I2C_MODE_SLAVE;
4328  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4329 
4330  /* Prepare transfer parameters */
4331  hi2c->pBuffPtr = pData;
4332  hi2c->XferCount = Size;
4333  hi2c->XferSize = hi2c->XferCount;
4334  hi2c->XferOptions = XferOptions;
4335 
4336  if (hi2c->hdmatx != NULL)
4337  {
4338  /* Set the I2C DMA transfer complete callback */
4339  hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
4340 
4341  /* Set the DMA error callback */
4342  hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4343 
4344  /* Set the unused DMA callbacks to NULL */
4345  hi2c->hdmatx->XferHalfCpltCallback = NULL;
4346  hi2c->hdmatx->XferAbortCallback = NULL;
4347 
4348  /* Enable the DMA stream */
4349  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
4350  }
4351  else
4352  {
4353  /* Update I2C state */
4354  hi2c->State = HAL_I2C_STATE_LISTEN;
4355  hi2c->Mode = HAL_I2C_MODE_NONE;
4356 
4357  /* Update I2C error code */
4358  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4359 
4360  /* Process Unlocked */
4361  __HAL_UNLOCK(hi2c);
4362 
4363  return HAL_ERROR;
4364  }
4365 
4366  if (dmaxferstatus == HAL_OK)
4367  {
4368  /* Enable Address Acknowledge */
4369  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4370 
4371  /* Clear ADDR flag */
4372  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4373 
4374  /* Process Unlocked */
4375  __HAL_UNLOCK(hi2c);
4376 
4377  /* Note : The I2C interrupts must be enabled after unlocking current process
4378  to avoid the risk of I2C interrupt handle execution before current
4379  process unlock */
4380  /* Enable EVT and ERR interrupt */
4381  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4382 
4383  /* Enable DMA Request */
4384  hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
4385 
4386  return HAL_OK;
4387  }
4388  else
4389  {
4390  /* Update I2C state */
4391  hi2c->State = HAL_I2C_STATE_READY;
4392  hi2c->Mode = HAL_I2C_MODE_NONE;
4393 
4394  /* Update I2C error code */
4395  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4396 
4397  /* Process Unlocked */
4398  __HAL_UNLOCK(hi2c);
4399 
4400  return HAL_ERROR;
4401  }
4402  }
4403  else
4404  {
4405  return HAL_BUSY;
4406  }
4407 }
4408 
4419 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4420 {
4421  /* Check the parameters */
4422  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4423 
4424  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4425  {
4426  if ((pData == NULL) || (Size == 0U))
4427  {
4428  return HAL_ERROR;
4429  }
4430 
4431  /* Process Locked */
4432  __HAL_LOCK(hi2c);
4433 
4434  /* Check if the I2C is already enabled */
4435  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4436  {
4437  /* Enable I2C peripheral */
4438  __HAL_I2C_ENABLE(hi2c);
4439  }
4440 
4441  /* Disable Pos */
4442  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4443 
4444  hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4445  hi2c->Mode = HAL_I2C_MODE_SLAVE;
4446  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4447 
4448  /* Prepare transfer parameters */
4449  hi2c->pBuffPtr = pData;
4450  hi2c->XferCount = Size;
4451  hi2c->XferSize = hi2c->XferCount;
4452  hi2c->XferOptions = XferOptions;
4453 
4454  /* Clear ADDR flag */
4455  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4456 
4457  /* Process Unlocked */
4458  __HAL_UNLOCK(hi2c);
4459 
4460  /* Note : The I2C interrupts must be enabled after unlocking current process
4461  to avoid the risk of I2C interrupt handle execution before current
4462  process unlock */
4463 
4464  /* Enable EVT, BUF and ERR interrupt */
4465  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4466 
4467  return HAL_OK;
4468  }
4469  else
4470  {
4471  return HAL_BUSY;
4472  }
4473 }
4474 
4485 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4486 {
4487  HAL_StatusTypeDef dmaxferstatus;
4488 
4489  /* Check the parameters */
4490  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4491 
4492  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4493  {
4494  if ((pData == NULL) || (Size == 0U))
4495  {
4496  return HAL_ERROR;
4497  }
4498 
4499  /* Process Locked */
4500  __HAL_LOCK(hi2c);
4501 
4502  /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4503  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4504 
4505  /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4506  /* and then toggle the HAL slave RX state to TX state */
4507  if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4508  {
4509  if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4510  {
4511  /* Abort DMA Xfer if any */
4512  if (hi2c->hdmarx != NULL)
4513  {
4514  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4515 
4516  /* Set the I2C DMA Abort callback :
4517  will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4518  hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4519 
4520  /* Abort DMA RX */
4521  if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4522  {
4523  /* Call Directly XferAbortCallback function in case of error */
4524  hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4525  }
4526  }
4527  }
4528  }
4529  else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4530  {
4531  if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4532  {
4533  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4534 
4535  /* Abort DMA Xfer if any */
4536  if (hi2c->hdmatx != NULL)
4537  {
4538  /* Set the I2C DMA Abort callback :
4539  will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4540  hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4541 
4542  /* Abort DMA TX */
4543  if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4544  {
4545  /* Call Directly XferAbortCallback function in case of error */
4546  hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4547  }
4548  }
4549  }
4550  }
4551  else
4552  {
4553  /* Nothing to do */
4554  }
4555 
4556  /* Check if the I2C is already enabled */
4557  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4558  {
4559  /* Enable I2C peripheral */
4560  __HAL_I2C_ENABLE(hi2c);
4561  }
4562 
4563  /* Disable Pos */
4564  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4565 
4566  hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4567  hi2c->Mode = HAL_I2C_MODE_SLAVE;
4568  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4569 
4570  /* Prepare transfer parameters */
4571  hi2c->pBuffPtr = pData;
4572  hi2c->XferCount = Size;
4573  hi2c->XferSize = hi2c->XferCount;
4574  hi2c->XferOptions = XferOptions;
4575 
4576  if (hi2c->hdmarx != NULL)
4577  {
4578  /* Set the I2C DMA transfer complete callback */
4579  hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
4580 
4581  /* Set the DMA error callback */
4582  hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4583 
4584  /* Set the unused DMA callbacks to NULL */
4585  hi2c->hdmarx->XferHalfCpltCallback = NULL;
4586  hi2c->hdmarx->XferAbortCallback = NULL;
4587 
4588  /* Enable the DMA stream */
4589  dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
4590  }
4591  else
4592  {
4593  /* Update I2C state */
4594  hi2c->State = HAL_I2C_STATE_LISTEN;
4595  hi2c->Mode = HAL_I2C_MODE_NONE;
4596 
4597  /* Update I2C error code */
4598  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4599 
4600  /* Process Unlocked */
4601  __HAL_UNLOCK(hi2c);
4602 
4603  return HAL_ERROR;
4604  }
4605 
4606  if (dmaxferstatus == HAL_OK)
4607  {
4608  /* Enable Address Acknowledge */
4609  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4610 
4611  /* Clear ADDR flag */
4612  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4613 
4614  /* Process Unlocked */
4615  __HAL_UNLOCK(hi2c);
4616 
4617  /* Enable DMA Request */
4618  SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4619 
4620  /* Note : The I2C interrupts must be enabled after unlocking current process
4621  to avoid the risk of I2C interrupt handle execution before current
4622  process unlock */
4623  /* Enable EVT and ERR interrupt */
4624  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4625 
4626  return HAL_OK;
4627  }
4628  else
4629  {
4630  /* Update I2C state */
4631  hi2c->State = HAL_I2C_STATE_READY;
4632  hi2c->Mode = HAL_I2C_MODE_NONE;
4633 
4634  /* Update I2C error code */
4635  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4636 
4637  /* Process Unlocked */
4638  __HAL_UNLOCK(hi2c);
4639 
4640  return HAL_ERROR;
4641  }
4642  }
4643  else
4644  {
4645  return HAL_BUSY;
4646  }
4647 }
4648 
4655 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4656 {
4657  if (hi2c->State == HAL_I2C_STATE_READY)
4658  {
4659  hi2c->State = HAL_I2C_STATE_LISTEN;
4660 
4661  /* Check if the I2C is already enabled */
4662  if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4663  {
4664  /* Enable I2C peripheral */
4665  __HAL_I2C_ENABLE(hi2c);
4666  }
4667 
4668  /* Enable Address Acknowledge */
4669  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4670 
4671  /* Enable EVT and ERR interrupt */
4672  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4673 
4674  return HAL_OK;
4675  }
4676  else
4677  {
4678  return HAL_BUSY;
4679  }
4680 }
4681 
4688 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4689 {
4690  /* Declaration of tmp to prevent undefined behavior of volatile usage */
4691  uint32_t tmp;
4692 
4693  /* Disable Address listen mode only if a transfer is not ongoing */
4694  if (hi2c->State == HAL_I2C_STATE_LISTEN)
4695  {
4696  tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4697  hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4698  hi2c->State = HAL_I2C_STATE_READY;
4699  hi2c->Mode = HAL_I2C_MODE_NONE;
4700 
4701  /* Disable Address Acknowledge */
4702  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4703 
4704  /* Disable EVT and ERR interrupt */
4705  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4706 
4707  return HAL_OK;
4708  }
4709  else
4710  {
4711  return HAL_BUSY;
4712  }
4713 }
4714 
4723 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4724 {
4725  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
4726  HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4727 
4728  /* Prevent unused argument(s) compilation warning */
4729  UNUSED(DevAddress);
4730 
4731  /* Abort Master transfer during Receive or Transmit process */
4732  if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && ((CurrentMode == HAL_I2C_MODE_MASTER) ||
4733  (CurrentMode == HAL_I2C_MODE_MEM)))
4734  {
4735  /* Process Locked */
4736  __HAL_LOCK(hi2c);
4737 
4738  hi2c->PreviousState = I2C_STATE_NONE;
4739  hi2c->State = HAL_I2C_STATE_ABORT;
4740 
4741  /* Disable Acknowledge */
4742  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4743 
4744  /* Generate Stop */
4745  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
4746 
4747  hi2c->XferCount = 0U;
4748 
4749  /* Disable EVT, BUF and ERR interrupt */
4750  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4751 
4752  /* Process Unlocked */
4753  __HAL_UNLOCK(hi2c);
4754 
4755  /* Call the corresponding callback to inform upper layer of End of Transfer */
4756  I2C_ITError(hi2c);
4757 
4758  return HAL_OK;
4759  }
4760  else
4761  {
4762  /* Wrong usage of abort function */
4763  /* This function should be used only in case of abort monitored by master device */
4764  /* Or periphal is not in busy state, mean there is no active sequence to be abort */
4765  return HAL_ERROR;
4766  }
4767 }
4768 
4783 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
4784 {
4785  uint32_t sr1itflags;
4786  uint32_t sr2itflags = 0U;
4787  uint32_t itsources = READ_REG(hi2c->Instance->CR2);
4788  uint32_t CurrentXferOptions = hi2c->XferOptions;
4789  HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4790  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
4791 
4792  /* Master or Memory mode selected */
4793  if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
4794  {
4795  sr2itflags = READ_REG(hi2c->Instance->SR2);
4796  sr1itflags = READ_REG(hi2c->Instance->SR1);
4797 
4798  /* Exit IRQ event until Start Bit detected in case of Other frame requested */
4799  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U))
4800  {
4801  return;
4802  }
4803 
4804  /* SB Set ----------------------------------------------------------------*/
4805  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4806  {
4807  /* Convert OTHER_xxx XferOptions if any */
4808  I2C_ConvertOtherXferOptions(hi2c);
4809 
4810  I2C_Master_SB(hi2c);
4811  }
4812  /* ADD10 Set -------------------------------------------------------------*/
4813  else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4814  {
4815  I2C_Master_ADD10(hi2c);
4816  }
4817  /* ADDR Set --------------------------------------------------------------*/
4818  else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4819  {
4820  I2C_Master_ADDR(hi2c);
4821  }
4822  /* I2C in mode Transmitter -----------------------------------------------*/
4823  else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET)
4824  {
4825  /* Do not check buffer and BTF flag if a Xfer DMA is on going */
4826  if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
4827  {
4828  /* TXE set and BTF reset -----------------------------------------------*/
4829  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4830  {
4831  I2C_MasterTransmit_TXE(hi2c);
4832  }
4833  /* BTF set -------------------------------------------------------------*/
4834  else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4835  {
4836  if (CurrentState == HAL_I2C_STATE_BUSY_TX)
4837  {
4838  I2C_MasterTransmit_BTF(hi2c);
4839  }
4840  else /* HAL_I2C_MODE_MEM */
4841  {
4842  if (CurrentMode == HAL_I2C_MODE_MEM)
4843  {
4844  I2C_MemoryTransmit_TXE_BTF(hi2c);
4845  }
4846  }
4847  }
4848  else
4849  {
4850  /* Do nothing */
4851  }
4852  }
4853  }
4854  /* I2C in mode Receiver --------------------------------------------------*/
4855  else
4856  {
4857  /* Do not check buffer and BTF flag if a Xfer DMA is on going */
4858  if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
4859  {
4860  /* RXNE set and BTF reset -----------------------------------------------*/
4861  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4862  {
4863  I2C_MasterReceive_RXNE(hi2c);
4864  }
4865  /* BTF set -------------------------------------------------------------*/
4866  else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4867  {
4868  I2C_MasterReceive_BTF(hi2c);
4869  }
4870  else
4871  {
4872  /* Do nothing */
4873  }
4874  }
4875  }
4876  }
4877  /* Slave mode selected */
4878  else
4879  {
4880  /* If an error is detected, read only SR1 register to prevent */
4881  /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */
4882  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4883  {
4884  sr1itflags = READ_REG(hi2c->Instance->SR1);
4885  }
4886  else
4887  {
4888  sr2itflags = READ_REG(hi2c->Instance->SR2);
4889  sr1itflags = READ_REG(hi2c->Instance->SR1);
4890  }
4891 
4892  /* ADDR set --------------------------------------------------------------*/
4893  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4894  {
4895  /* Now time to read SR2, this will clear ADDR flag automatically */
4896  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4897  {
4898  sr2itflags = READ_REG(hi2c->Instance->SR2);
4899  }
4900  I2C_Slave_ADDR(hi2c, sr2itflags);
4901  }
4902  /* STOPF set --------------------------------------------------------------*/
4903  else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4904  {
4905  I2C_Slave_STOPF(hi2c);
4906  }
4907  /* I2C in mode Transmitter -----------------------------------------------*/
4908  else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
4909  {
4910  /* TXE set and BTF reset -----------------------------------------------*/
4911  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4912  {
4913  I2C_SlaveTransmit_TXE(hi2c);
4914  }
4915  /* BTF set -------------------------------------------------------------*/
4916  else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4917  {
4918  I2C_SlaveTransmit_BTF(hi2c);
4919  }
4920  else
4921  {
4922  /* Do nothing */
4923  }
4924  }
4925  /* I2C in mode Receiver --------------------------------------------------*/
4926  else
4927  {
4928  /* RXNE set and BTF reset ----------------------------------------------*/
4929  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4930  {
4931  I2C_SlaveReceive_RXNE(hi2c);
4932  }
4933  /* BTF set -------------------------------------------------------------*/
4934  else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4935  {
4936  I2C_SlaveReceive_BTF(hi2c);
4937  }
4938  else
4939  {
4940  /* Do nothing */
4941  }
4942  }
4943  }
4944 }
4945 
4952 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4953 {
4954  HAL_I2C_ModeTypeDef tmp1;
4955  uint32_t tmp2;
4956  HAL_I2C_StateTypeDef tmp3;
4957  uint32_t tmp4;
4958  uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
4959  uint32_t itsources = READ_REG(hi2c->Instance->CR2);
4960  uint32_t error = HAL_I2C_ERROR_NONE;
4961  HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4962 
4963  /* I2C Bus error interrupt occurred ----------------------------------------*/
4964  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4965  {
4966  error |= HAL_I2C_ERROR_BERR;
4967 
4968  /* Clear BERR flag */
4969  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4970  }
4971 
4972  /* I2C Arbitration Lost error interrupt occurred ---------------------------*/
4973  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4974  {
4975  error |= HAL_I2C_ERROR_ARLO;
4976 
4977  /* Clear ARLO flag */
4978  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4979  }
4980 
4981  /* I2C Acknowledge failure error interrupt occurred ------------------------*/
4982  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4983  {
4984  tmp1 = CurrentMode;
4985  tmp2 = hi2c->XferCount;
4986  tmp3 = hi2c->State;
4987  tmp4 = hi2c->PreviousState;
4988  if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
4989  ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
4990  ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
4991  {
4992  I2C_Slave_AF(hi2c);
4993  }
4994  else
4995  {
4996  /* Clear AF flag */
4997  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4998 
4999  error |= HAL_I2C_ERROR_AF;
5000 
5001  /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
5002  if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
5003  {
5004  /* Generate Stop */
5005  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5006  }
5007  }
5008  }
5009 
5010  /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
5011  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
5012  {
5013  error |= HAL_I2C_ERROR_OVR;
5014  /* Clear OVR flag */
5015  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
5016  }
5017 
5018  /* Call the Error Callback in case of Error detected -----------------------*/
5019  if (error != HAL_I2C_ERROR_NONE)
5020  {
5021  hi2c->ErrorCode |= error;
5022  I2C_ITError(hi2c);
5023  }
5024 }
5025 
5032 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
5033 {
5034  /* Prevent unused argument(s) compilation warning */
5035  UNUSED(hi2c);
5036 
5037  /* NOTE : This function should not be modified, when the callback is needed,
5038  the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
5039  */
5040 }
5041 
5048 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
5049 {
5050  /* Prevent unused argument(s) compilation warning */
5051  UNUSED(hi2c);
5052 
5053  /* NOTE : This function should not be modified, when the callback is needed,
5054  the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
5055  */
5056 }
5057 
5063 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
5064 {
5065  /* Prevent unused argument(s) compilation warning */
5066  UNUSED(hi2c);
5067 
5068  /* NOTE : This function should not be modified, when the callback is needed,
5069  the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
5070  */
5071 }
5072 
5079 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
5080 {
5081  /* Prevent unused argument(s) compilation warning */
5082  UNUSED(hi2c);
5083 
5084  /* NOTE : This function should not be modified, when the callback is needed,
5085  the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
5086  */
5087 }
5088 
5097 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
5098 {
5099  /* Prevent unused argument(s) compilation warning */
5100  UNUSED(hi2c);
5101  UNUSED(TransferDirection);
5102  UNUSED(AddrMatchCode);
5103 
5104  /* NOTE : This function should not be modified, when the callback is needed,
5105  the HAL_I2C_AddrCallback() could be implemented in the user file
5106  */
5107 }
5108 
5115 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
5116 {
5117  /* Prevent unused argument(s) compilation warning */
5118  UNUSED(hi2c);
5119 
5120  /* NOTE : This function should not be modified, when the callback is needed,
5121  the HAL_I2C_ListenCpltCallback() could be implemented in the user file
5122  */
5123 }
5124 
5131 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
5132 {
5133  /* Prevent unused argument(s) compilation warning */
5134  UNUSED(hi2c);
5135 
5136  /* NOTE : This function should not be modified, when the callback is needed,
5137  the HAL_I2C_MemTxCpltCallback could be implemented in the user file
5138  */
5139 }
5140 
5147 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
5148 {
5149  /* Prevent unused argument(s) compilation warning */
5150  UNUSED(hi2c);
5151 
5152  /* NOTE : This function should not be modified, when the callback is needed,
5153  the HAL_I2C_MemRxCpltCallback could be implemented in the user file
5154  */
5155 }
5156 
5163 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
5164 {
5165  /* Prevent unused argument(s) compilation warning */
5166  UNUSED(hi2c);
5167 
5168  /* NOTE : This function should not be modified, when the callback is needed,
5169  the HAL_I2C_ErrorCallback could be implemented in the user file
5170  */
5171 }
5172 
5179 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
5180 {
5181  /* Prevent unused argument(s) compilation warning */
5182  UNUSED(hi2c);
5183 
5184  /* NOTE : This function should not be modified, when the callback is needed,
5185  the HAL_I2C_AbortCpltCallback could be implemented in the user file
5186  */
5187 }
5188 
5214 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
5215 {
5216  /* Return I2C handle state */
5217  return hi2c->State;
5218 }
5219 
5226 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
5227 {
5228  return hi2c->Mode;
5229 }
5230 
5237 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
5238 {
5239  return hi2c->ErrorCode;
5240 }
5241 
5260 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
5261 {
5262  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5263  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5264  HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
5265  uint32_t CurrentXferOptions = hi2c->XferOptions;
5266 
5267  if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5268  {
5269  /* Call TxCpltCallback() directly if no stop mode is set */
5270  if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
5271  {
5272  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5273 
5274  hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5275  hi2c->Mode = HAL_I2C_MODE_NONE;
5276  hi2c->State = HAL_I2C_STATE_READY;
5277 
5278 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5279  hi2c->MasterTxCpltCallback(hi2c);
5280 #else
5281  HAL_I2C_MasterTxCpltCallback(hi2c);
5282 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5283  }
5284  else /* Generate Stop condition then Call TxCpltCallback() */
5285  {
5286  /* Disable EVT, BUF and ERR interrupt */
5287  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5288 
5289  /* Generate Stop */
5290  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5291 
5292  hi2c->PreviousState = I2C_STATE_NONE;
5293  hi2c->State = HAL_I2C_STATE_READY;
5294 
5295  if (hi2c->Mode == HAL_I2C_MODE_MEM)
5296  {
5297  hi2c->Mode = HAL_I2C_MODE_NONE;
5298 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5299  hi2c->MemTxCpltCallback(hi2c);
5300 #else
5301  HAL_I2C_MemTxCpltCallback(hi2c);
5302 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5303  }
5304  else
5305  {
5306  hi2c->Mode = HAL_I2C_MODE_NONE;
5307 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5308  hi2c->MasterTxCpltCallback(hi2c);
5309 #else
5310  HAL_I2C_MasterTxCpltCallback(hi2c);
5311 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5312  }
5313  }
5314  }
5315  else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
5316  ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
5317  {
5318  if (hi2c->XferCount == 0U)
5319  {
5320  /* Disable BUF interrupt */
5321  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5322  }
5323  else
5324  {
5325  if (hi2c->Mode == HAL_I2C_MODE_MEM)
5326  {
5327  I2C_MemoryTransmit_TXE_BTF(hi2c);
5328  }
5329  else
5330  {
5331  /* Write data to DR */
5332  hi2c->Instance->DR = *hi2c->pBuffPtr;
5333 
5334  /* Increment Buffer pointer */
5335  hi2c->pBuffPtr++;
5336 
5337  /* Update counter */
5338  hi2c->XferCount--;
5339  }
5340  }
5341  }
5342  else
5343  {
5344  /* Do nothing */
5345  }
5346 }
5347 
5354 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
5355 {
5356  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5357  uint32_t CurrentXferOptions = hi2c->XferOptions;
5358 
5359  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5360  {
5361  if (hi2c->XferCount != 0U)
5362  {
5363  /* Write data to DR */
5364  hi2c->Instance->DR = *hi2c->pBuffPtr;
5365 
5366  /* Increment Buffer pointer */
5367  hi2c->pBuffPtr++;
5368 
5369  /* Update counter */
5370  hi2c->XferCount--;
5371  }
5372  else
5373  {
5374  /* Call TxCpltCallback() directly if no stop mode is set */
5375  if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
5376  {
5377  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5378 
5379  hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5380  hi2c->Mode = HAL_I2C_MODE_NONE;
5381  hi2c->State = HAL_I2C_STATE_READY;
5382 
5383 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5384  hi2c->MasterTxCpltCallback(hi2c);
5385 #else
5386  HAL_I2C_MasterTxCpltCallback(hi2c);
5387 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5388  }
5389  else /* Generate Stop condition then Call TxCpltCallback() */
5390  {
5391  /* Disable EVT, BUF and ERR interrupt */
5392  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5393 
5394  /* Generate Stop */
5395  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5396 
5397  hi2c->PreviousState = I2C_STATE_NONE;
5398  hi2c->State = HAL_I2C_STATE_READY;
5399  if (hi2c->Mode == HAL_I2C_MODE_MEM)
5400  {
5401  hi2c->Mode = HAL_I2C_MODE_NONE;
5402 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5403  hi2c->MemTxCpltCallback(hi2c);
5404 #else
5405  HAL_I2C_MemTxCpltCallback(hi2c);
5406 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5407  }
5408  else
5409  {
5410  hi2c->Mode = HAL_I2C_MODE_NONE;
5411 
5412 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5413  hi2c->MasterTxCpltCallback(hi2c);
5414 #else
5415  HAL_I2C_MasterTxCpltCallback(hi2c);
5416 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5417  }
5418  }
5419  }
5420  }
5421  else
5422  {
5423  /* Do nothing */
5424  }
5425 }
5426 
5433 static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c)
5434 {
5435  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5436  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5437 
5438  if (hi2c->EventCount == 0U)
5439  {
5440  /* If Memory address size is 8Bit */
5441  if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
5442  {
5443  /* Send Memory Address */
5444  hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
5445 
5446  hi2c->EventCount += 2U;
5447  }
5448  /* If Memory address size is 16Bit */
5449  else
5450  {
5451  /* Send MSB of Memory Address */
5452  hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
5453 
5454  hi2c->EventCount++;
5455  }
5456  }
5457  else if (hi2c->EventCount == 1U)
5458  {
5459  /* Send LSB of Memory Address */
5460  hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
5461 
5462  hi2c->EventCount++;
5463  }
5464  else if (hi2c->EventCount == 2U)
5465  {
5466  if (CurrentState == HAL_I2C_STATE_BUSY_RX)
5467  {
5468  /* Generate Restart */
5469  hi2c->Instance->CR1 |= I2C_CR1_START;
5470 
5471  hi2c->EventCount++;
5472  }
5473  else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5474  {
5475  /* Write data to DR */
5476  hi2c->Instance->DR = *hi2c->pBuffPtr;
5477 
5478  /* Increment Buffer pointer */
5479  hi2c->pBuffPtr++;
5480 
5481  /* Update counter */
5482  hi2c->XferCount--;
5483  }
5484  else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5485  {
5486  /* Generate Stop condition then Call TxCpltCallback() */
5487  /* Disable EVT, BUF and ERR interrupt */
5488  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5489 
5490  /* Generate Stop */
5491  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5492 
5493  hi2c->PreviousState = I2C_STATE_NONE;
5494  hi2c->State = HAL_I2C_STATE_READY;
5495  hi2c->Mode = HAL_I2C_MODE_NONE;
5496 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5497  hi2c->MemTxCpltCallback(hi2c);
5498 #else
5499  HAL_I2C_MemTxCpltCallback(hi2c);
5500 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5501  }
5502  else
5503  {
5504  /* Do nothing */
5505  }
5506  }
5507  else
5508  {
5509  /* Clear TXE and BTF flags */
5510  I2C_Flush_DR(hi2c);
5511  }
5512 }
5513 
5520 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
5521 {
5522  if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5523  {
5524  uint32_t tmp;
5525  uint32_t CurrentXferOptions;
5526 
5527  CurrentXferOptions = hi2c->XferOptions;
5528  tmp = hi2c->XferCount;
5529  if (tmp > 3U)
5530  {
5531  /* Read data from DR */
5532  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5533 
5534  /* Increment Buffer pointer */
5535  hi2c->pBuffPtr++;
5536 
5537  /* Update counter */
5538  hi2c->XferCount--;
5539 
5540  if (hi2c->XferCount == (uint16_t)3)
5541  {
5542  /* Disable BUF interrupt, this help to treat correctly the last 4 bytes
5543  on BTF subroutine */
5544  /* Disable BUF interrupt */
5545  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5546  }
5547  }
5548  else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U)))
5549  {
5550  if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK)
5551  {
5552  /* Disable Acknowledge */
5553  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5554 
5555  /* Disable EVT, BUF and ERR interrupt */
5556  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5557 
5558  /* Read data from DR */
5559  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5560 
5561  /* Increment Buffer pointer */
5562  hi2c->pBuffPtr++;
5563 
5564  /* Update counter */
5565  hi2c->XferCount--;
5566 
5567  hi2c->State = HAL_I2C_STATE_READY;
5568 
5569  if (hi2c->Mode == HAL_I2C_MODE_MEM)
5570  {
5571  hi2c->Mode = HAL_I2C_MODE_NONE;
5572  hi2c->PreviousState = I2C_STATE_NONE;
5573 
5574 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5575  hi2c->MemRxCpltCallback(hi2c);
5576 #else
5577  HAL_I2C_MemRxCpltCallback(hi2c);
5578 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5579  }
5580  else
5581  {
5582  hi2c->Mode = HAL_I2C_MODE_NONE;
5583  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
5584  {
5585  hi2c->PreviousState = I2C_STATE_NONE;
5586  }
5587  else
5588  {
5589  hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5590  }
5591 
5592 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5593  hi2c->MasterRxCpltCallback(hi2c);
5594 #else
5595  HAL_I2C_MasterRxCpltCallback(hi2c);
5596 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5597  }
5598  }
5599  else
5600  {
5601  /* Disable EVT, BUF and ERR interrupt */
5602  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5603 
5604  /* Read data from DR */
5605  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5606 
5607  /* Increment Buffer pointer */
5608  hi2c->pBuffPtr++;
5609 
5610  /* Update counter */
5611  hi2c->XferCount--;
5612 
5613  hi2c->State = HAL_I2C_STATE_READY;
5614  hi2c->Mode = HAL_I2C_MODE_NONE;
5615 
5616  /* Call user error callback */
5617 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5618  hi2c->ErrorCallback(hi2c);
5619 #else
5620  HAL_I2C_ErrorCallback(hi2c);
5621 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5622  }
5623  }
5624  else
5625  {
5626  /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5627  on BTF subroutine if there is a reception delay between N-1 and N byte */
5628  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5629  }
5630  }
5631 }
5632 
5639 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
5640 {
5641  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5642  uint32_t CurrentXferOptions = hi2c->XferOptions;
5643 
5644  if (hi2c->XferCount == 4U)
5645  {
5646  /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5647  on BTF subroutine if there is a reception delay between N-1 and N byte */
5648  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5649 
5650  /* Read data from DR */
5651  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5652 
5653  /* Increment Buffer pointer */
5654  hi2c->pBuffPtr++;
5655 
5656  /* Update counter */
5657  hi2c->XferCount--;
5658  }
5659  else if (hi2c->XferCount == 3U)
5660  {
5661  /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5662  on BTF subroutine if there is a reception delay between N-1 and N byte */
5663  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5664 
5665  if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME))
5666  {
5667  /* Disable Acknowledge */
5668  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5669  }
5670 
5671  /* Read data from DR */
5672  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5673 
5674  /* Increment Buffer pointer */
5675  hi2c->pBuffPtr++;
5676 
5677  /* Update counter */
5678  hi2c->XferCount--;
5679  }
5680  else if (hi2c->XferCount == 2U)
5681  {
5682  /* Prepare next transfer or stop current transfer */
5683  if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP))
5684  {
5685  /* Disable Acknowledge */
5686  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5687  }
5688  else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME))
5689  {
5690  /* Enable Acknowledge */
5691  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5692  }
5693  else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)
5694  {
5695  /* Generate Stop */
5696  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5697  }
5698  else
5699  {
5700  /* Do nothing */
5701  }
5702 
5703  /* Read data from DR */
5704  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5705 
5706  /* Increment Buffer pointer */
5707  hi2c->pBuffPtr++;
5708 
5709  /* Update counter */
5710  hi2c->XferCount--;
5711 
5712  /* Read data from DR */
5713  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5714 
5715  /* Increment Buffer pointer */
5716  hi2c->pBuffPtr++;
5717 
5718  /* Update counter */
5719  hi2c->XferCount--;
5720 
5721  /* Disable EVT and ERR interrupt */
5722  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
5723 
5724  hi2c->State = HAL_I2C_STATE_READY;
5725  if (hi2c->Mode == HAL_I2C_MODE_MEM)
5726  {
5727  hi2c->Mode = HAL_I2C_MODE_NONE;
5728  hi2c->PreviousState = I2C_STATE_NONE;
5729 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5730  hi2c->MemRxCpltCallback(hi2c);
5731 #else
5732  HAL_I2C_MemRxCpltCallback(hi2c);
5733 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5734  }
5735  else
5736  {
5737  hi2c->Mode = HAL_I2C_MODE_NONE;
5738  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
5739  {
5740  hi2c->PreviousState = I2C_STATE_NONE;
5741  }
5742  else
5743  {
5744  hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5745  }
5746 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5747  hi2c->MasterRxCpltCallback(hi2c);
5748 #else
5749  HAL_I2C_MasterRxCpltCallback(hi2c);
5750 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5751  }
5752  }
5753  else
5754  {
5755  /* Read data from DR */
5756  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5757 
5758  /* Increment Buffer pointer */
5759  hi2c->pBuffPtr++;
5760 
5761  /* Update counter */
5762  hi2c->XferCount--;
5763  }
5764 }
5765 
5772 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c)
5773 {
5774  if (hi2c->Mode == HAL_I2C_MODE_MEM)
5775  {
5776  if (hi2c->EventCount == 0U)
5777  {
5778  /* Send slave address */
5779  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
5780  }
5781  else
5782  {
5783  hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
5784  }
5785  }
5786  else
5787  {
5788  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
5789  {
5790  /* Send slave 7 Bits address */
5791  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5792  {
5793  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
5794  }
5795  else
5796  {
5797  hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
5798  }
5799 
5800  if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
5801  || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
5802  {
5803  /* Enable DMA Request */
5804  SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5805  }
5806  }
5807  else
5808  {
5809  if (hi2c->EventCount == 0U)
5810  {
5811  /* Send header of slave address */
5812  hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
5813  }
5814  else if (hi2c->EventCount == 1U)
5815  {
5816  /* Send header of slave address */
5817  hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
5818  }
5819  else
5820  {
5821  /* Do nothing */
5822  }
5823  }
5824  }
5825 }
5826 
5833 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
5834 {
5835  /* Send slave address */
5836  hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
5837 
5838  if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
5839  || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
5840  {
5841  /* Enable DMA Request */
5842  SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5843  }
5844 }
5845 
5852 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
5853 {
5854  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
5855  HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
5856  uint32_t CurrentXferOptions = hi2c->XferOptions;
5857  uint32_t Prev_State = hi2c->PreviousState;
5858 
5859  if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5860  {
5861  if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
5862  {
5863  /* Clear ADDR flag */
5864  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5865  }
5866  else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
5867  {
5868  /* Clear ADDR flag */
5869  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5870 
5871  /* Generate Restart */
5872  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
5873 
5874  hi2c->EventCount++;
5875  }
5876  else
5877  {
5878  if (hi2c->XferCount == 0U)
5879  {
5880  /* Clear ADDR flag */
5881  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5882 
5883  /* Generate Stop */
5884  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5885  }
5886  else if (hi2c->XferCount == 1U)
5887  {
5888  if (CurrentXferOptions == I2C_NO_OPTION_FRAME)
5889  {
5890  /* Disable Acknowledge */
5891  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5892 
5893  if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
5894  {
5895  /* Disable Acknowledge */
5896  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5897 
5898  /* Clear ADDR flag */
5899  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5900  }
5901  else
5902  {
5903  /* Clear ADDR flag */
5904  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5905 
5906  /* Generate Stop */
5907  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5908  }
5909  }
5910  /* Prepare next transfer or stop current transfer */
5911  else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
5912  && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME)))
5913  {
5914  if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
5915  {
5916  /* Disable Acknowledge */
5917  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5918  }
5919  else
5920  {
5921  /* Enable Acknowledge */
5922  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5923  }
5924 
5925  /* Clear ADDR flag */
5926  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5927  }
5928  else
5929  {
5930  /* Disable Acknowledge */
5931  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5932 
5933  /* Clear ADDR flag */
5934  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5935 
5936  /* Generate Stop */
5937  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5938  }
5939  }
5940  else if (hi2c->XferCount == 2U)
5941  {
5942  if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
5943  {
5944  /* Disable Acknowledge */
5945  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5946 
5947  /* Enable Pos */
5948  SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
5949  }
5950  else
5951  {
5952  /* Enable Acknowledge */
5953  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5954  }
5955 
5956  if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
5957  {
5958  /* Enable Last DMA bit */
5959  SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
5960  }
5961 
5962  /* Clear ADDR flag */
5963  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5964  }
5965  else
5966  {
5967  /* Enable Acknowledge */
5968  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5969 
5970  if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
5971  {
5972  /* Enable Last DMA bit */
5973  SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
5974  }
5975 
5976  /* Clear ADDR flag */
5977  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5978  }
5979 
5980  /* Reset Event counter */
5981  hi2c->EventCount = 0U;
5982  }
5983  }
5984  else
5985  {
5986  /* Clear ADDR flag */
5987  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5988  }
5989 }
5990 
5997 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
5998 {
5999  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
6000  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6001 
6002  if (hi2c->XferCount != 0U)
6003  {
6004  /* Write data to DR */
6005  hi2c->Instance->DR = *hi2c->pBuffPtr;
6006 
6007  /* Increment Buffer pointer */
6008  hi2c->pBuffPtr++;
6009 
6010  /* Update counter */
6011  hi2c->XferCount--;
6012 
6013  if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
6014  {
6015  /* Last Byte is received, disable Interrupt */
6016  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
6017 
6018  /* Set state at HAL_I2C_STATE_LISTEN */
6019  hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6020  hi2c->State = HAL_I2C_STATE_LISTEN;
6021 
6022  /* Call the corresponding callback to inform upper layer of End of Transfer */
6023 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6024  hi2c->SlaveTxCpltCallback(hi2c);
6025 #else
6026  HAL_I2C_SlaveTxCpltCallback(hi2c);
6027 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6028  }
6029  }
6030 }
6031 
6038 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
6039 {
6040  if (hi2c->XferCount != 0U)
6041  {
6042  /* Write data to DR */
6043  hi2c->Instance->DR = *hi2c->pBuffPtr;
6044 
6045  /* Increment Buffer pointer */
6046  hi2c->pBuffPtr++;
6047 
6048  /* Update counter */
6049  hi2c->XferCount--;
6050  }
6051 }
6052 
6059 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
6060 {
6061  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
6062  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6063 
6064  if (hi2c->XferCount != 0U)
6065  {
6066  /* Read data from DR */
6067  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6068 
6069  /* Increment Buffer pointer */
6070  hi2c->pBuffPtr++;
6071 
6072  /* Update counter */
6073  hi2c->XferCount--;
6074 
6075  if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
6076  {
6077  /* Last Byte is received, disable Interrupt */
6078  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
6079 
6080  /* Set state at HAL_I2C_STATE_LISTEN */
6081  hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6082  hi2c->State = HAL_I2C_STATE_LISTEN;
6083 
6084  /* Call the corresponding callback to inform upper layer of End of Transfer */
6085 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6086  hi2c->SlaveRxCpltCallback(hi2c);
6087 #else
6088  HAL_I2C_SlaveRxCpltCallback(hi2c);
6089 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6090  }
6091  }
6092 }
6093 
6100 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
6101 {
6102  if (hi2c->XferCount != 0U)
6103  {
6104  /* Read data from DR */
6105  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6106 
6107  /* Increment Buffer pointer */
6108  hi2c->pBuffPtr++;
6109 
6110  /* Update counter */
6111  hi2c->XferCount--;
6112  }
6113 }
6114 
6122 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags)
6123 {
6124  uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
6125  uint16_t SlaveAddrCode;
6126 
6127  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6128  {
6129  /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */
6130  __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF));
6131 
6132  /* Transfer Direction requested by Master */
6133  if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET)
6134  {
6135  TransferDirection = I2C_DIRECTION_TRANSMIT;
6136  }
6137 
6138  if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET)
6139  {
6140  SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1;
6141  }
6142  else
6143  {
6144  SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2;
6145  }
6146 
6147  /* Process Unlocked */
6148  __HAL_UNLOCK(hi2c);
6149 
6150  /* Call Slave Addr callback */
6151 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6152  hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
6153 #else
6154  HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
6155 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6156  }
6157  else
6158  {
6159  /* Clear ADDR flag */
6160  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6161 
6162  /* Process Unlocked */
6163  __HAL_UNLOCK(hi2c);
6164  }
6165 }
6166 
6173 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
6174 {
6175  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6176  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6177 
6178  /* Disable EVT, BUF and ERR interrupt */
6179  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6180 
6181  /* Clear STOPF flag */
6182  __HAL_I2C_CLEAR_STOPFLAG(hi2c);
6183 
6184  /* Disable Acknowledge */
6185  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6186 
6187  /* If a DMA is ongoing, Update handle size context */
6188  if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
6189  {
6190  if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
6191  {
6192  hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx));
6193 
6194  if (hi2c->XferCount != 0U)
6195  {
6196  /* Set ErrorCode corresponding to a Non-Acknowledge */
6197  hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6198  }
6199 
6200  /* Disable, stop the current DMA */
6201  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6202 
6203  /* Abort DMA Xfer if any */
6204  if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6205  {
6206  /* Set the I2C DMA Abort callback :
6207  will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6208  hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6209 
6210  /* Abort DMA RX */
6211  if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6212  {
6213  /* Call Directly XferAbortCallback function in case of error */
6214  hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6215  }
6216  }
6217  }
6218  else
6219  {
6220  hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx));
6221 
6222  if (hi2c->XferCount != 0U)
6223  {
6224  /* Set ErrorCode corresponding to a Non-Acknowledge */
6225  hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6226  }
6227 
6228  /* Disable, stop the current DMA */
6229  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6230 
6231  /* Abort DMA Xfer if any */
6232  if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6233  {
6234  /* Set the I2C DMA Abort callback :
6235  will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6236  hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6237 
6238  /* Abort DMA TX */
6239  if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6240  {
6241  /* Call Directly XferAbortCallback function in case of error */
6242  hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6243  }
6244  }
6245  }
6246  }
6247 
6248  /* All data are not transferred, so set error code accordingly */
6249  if (hi2c->XferCount != 0U)
6250  {
6251  /* Store Last receive data if any */
6252  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
6253  {
6254  /* Read data from DR */
6255  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6256 
6257  /* Increment Buffer pointer */
6258  hi2c->pBuffPtr++;
6259 
6260  /* Update counter */
6261  hi2c->XferCount--;
6262  }
6263 
6264  /* Store Last receive data if any */
6265  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6266  {
6267  /* Read data from DR */
6268  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6269 
6270  /* Increment Buffer pointer */
6271  hi2c->pBuffPtr++;
6272 
6273  /* Update counter */
6274  hi2c->XferCount--;
6275  }
6276 
6277  if (hi2c->XferCount != 0U)
6278  {
6279  /* Set ErrorCode corresponding to a Non-Acknowledge */
6280  hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6281  }
6282  }
6283 
6284  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6285  {
6286  /* Call the corresponding callback to inform upper layer of End of Transfer */
6287  I2C_ITError(hi2c);
6288  }
6289  else
6290  {
6291  if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
6292  {
6293  /* Set state at HAL_I2C_STATE_LISTEN */
6294  hi2c->PreviousState = I2C_STATE_NONE;
6295  hi2c->State = HAL_I2C_STATE_LISTEN;
6296 
6297  /* Call the corresponding callback to inform upper layer of End of Transfer */
6298 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6299  hi2c->SlaveRxCpltCallback(hi2c);
6300 #else
6301  HAL_I2C_SlaveRxCpltCallback(hi2c);
6302 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6303  }
6304 
6305  if (hi2c->State == HAL_I2C_STATE_LISTEN)
6306  {
6307  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6308  hi2c->PreviousState = I2C_STATE_NONE;
6309  hi2c->State = HAL_I2C_STATE_READY;
6310  hi2c->Mode = HAL_I2C_MODE_NONE;
6311 
6312  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6313 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6314  hi2c->ListenCpltCallback(hi2c);
6315 #else
6316  HAL_I2C_ListenCpltCallback(hi2c);
6317 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6318  }
6319  else
6320  {
6321  if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
6322  {
6323  hi2c->PreviousState = I2C_STATE_NONE;
6324  hi2c->State = HAL_I2C_STATE_READY;
6325  hi2c->Mode = HAL_I2C_MODE_NONE;
6326 
6327 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6328  hi2c->SlaveRxCpltCallback(hi2c);
6329 #else
6330  HAL_I2C_SlaveRxCpltCallback(hi2c);
6331 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6332  }
6333  }
6334  }
6335 }
6336 
6342 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
6343 {
6344  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
6345  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6346  uint32_t CurrentXferOptions = hi2c->XferOptions;
6347 
6348  if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
6349  (CurrentState == HAL_I2C_STATE_LISTEN))
6350  {
6351  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6352 
6353  /* Disable EVT, BUF and ERR interrupt */
6354  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6355 
6356  /* Clear AF flag */
6357  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6358 
6359  /* Disable Acknowledge */
6360  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6361 
6362  hi2c->PreviousState = I2C_STATE_NONE;
6363  hi2c->State = HAL_I2C_STATE_READY;
6364  hi2c->Mode = HAL_I2C_MODE_NONE;
6365 
6366  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6367 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6368  hi2c->ListenCpltCallback(hi2c);
6369 #else
6370  HAL_I2C_ListenCpltCallback(hi2c);
6371 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6372  }
6373  else if (CurrentState == HAL_I2C_STATE_BUSY_TX)
6374  {
6375  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6376  hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6377  hi2c->State = HAL_I2C_STATE_READY;
6378  hi2c->Mode = HAL_I2C_MODE_NONE;
6379 
6380  /* Disable EVT, BUF and ERR interrupt */
6381  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6382 
6383  /* Clear AF flag */
6384  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6385 
6386  /* Disable Acknowledge */
6387  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6388 
6389  /* Clear TXE flag */
6390  I2C_Flush_DR(hi2c);
6391 
6392 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6393  hi2c->SlaveTxCpltCallback(hi2c);
6394 #else
6395  HAL_I2C_SlaveTxCpltCallback(hi2c);
6396 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6397  }
6398  else
6399  {
6400  /* Clear AF flag only */
6401  /* State Listen, but XferOptions == FIRST or NEXT */
6402  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6403  }
6404 }
6405 
6411 static void I2C_ITError(I2C_HandleTypeDef *hi2c)
6412 {
6413  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6414  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6415  HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
6416  uint32_t CurrentError;
6417 
6418  if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
6419  {
6420  /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
6421  hi2c->Instance->CR1 &= ~I2C_CR1_POS;
6422  }
6423 
6424  if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6425  {
6426  /* keep HAL_I2C_STATE_LISTEN */
6427  hi2c->PreviousState = I2C_STATE_NONE;
6428  hi2c->State = HAL_I2C_STATE_LISTEN;
6429  }
6430  else
6431  {
6432  /* If state is an abort treatment on going, don't change state */
6433  /* This change will be do later */
6434  if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT))
6435  {
6436  hi2c->State = HAL_I2C_STATE_READY;
6437  hi2c->Mode = HAL_I2C_MODE_NONE;
6438  }
6439  hi2c->PreviousState = I2C_STATE_NONE;
6440  }
6441 
6442  /* Abort DMA transfer */
6443  if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
6444  {
6445  hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
6446 
6447  if (hi2c->hdmatx->State != HAL_DMA_STATE_READY)
6448  {
6449  /* Set the DMA Abort callback :
6450  will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6451  hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6452 
6453  if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6454  {
6455  /* Disable I2C peripheral to prevent dummy data in buffer */
6456  __HAL_I2C_DISABLE(hi2c);
6457 
6458  hi2c->State = HAL_I2C_STATE_READY;
6459 
6460  /* Call Directly XferAbortCallback function in case of error */
6461  hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6462  }
6463  }
6464  else
6465  {
6466  /* Set the DMA Abort callback :
6467  will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6468  hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6469 
6470  if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6471  {
6472  /* Store Last receive data if any */
6473  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6474  {
6475  /* Read data from DR */
6476  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6477 
6478  /* Increment Buffer pointer */
6479  hi2c->pBuffPtr++;
6480  }
6481 
6482  /* Disable I2C peripheral to prevent dummy data in buffer */
6483  __HAL_I2C_DISABLE(hi2c);
6484 
6485  hi2c->State = HAL_I2C_STATE_READY;
6486 
6487  /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6488  hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6489  }
6490  }
6491  }
6492  else if (hi2c->State == HAL_I2C_STATE_ABORT)
6493  {
6494  hi2c->State = HAL_I2C_STATE_READY;
6495  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
6496 
6497  /* Store Last receive data if any */
6498  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6499  {
6500  /* Read data from DR */
6501  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6502 
6503  /* Increment Buffer pointer */
6504  hi2c->pBuffPtr++;
6505  }
6506 
6507  /* Disable I2C peripheral to prevent dummy data in buffer */
6508  __HAL_I2C_DISABLE(hi2c);
6509 
6510  /* Call the corresponding callback to inform upper layer of End of Transfer */
6511 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6512  hi2c->AbortCpltCallback(hi2c);
6513 #else
6514  HAL_I2C_AbortCpltCallback(hi2c);
6515 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6516  }
6517  else
6518  {
6519  /* Store Last receive data if any */
6520  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6521  {
6522  /* Read data from DR */
6523  *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6524 
6525  /* Increment Buffer pointer */
6526  hi2c->pBuffPtr++;
6527  }
6528 
6529  /* Call user error callback */
6530 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6531  hi2c->ErrorCallback(hi2c);
6532 #else
6533  HAL_I2C_ErrorCallback(hi2c);
6534 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6535  }
6536 
6537  /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */
6538  CurrentError = hi2c->ErrorCode;
6539 
6540  if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \
6541  ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \
6542  ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \
6543  ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR))
6544  {
6545  /* Disable EVT, BUF and ERR interrupt */
6546  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6547  }
6548 
6549  /* So may inform upper layer that listen phase is stopped */
6550  /* during NACK error treatment */
6551  CurrentState = hi2c->State;
6552  if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN))
6553  {
6554  hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6555  hi2c->PreviousState = I2C_STATE_NONE;
6556  hi2c->State = HAL_I2C_STATE_READY;
6557  hi2c->Mode = HAL_I2C_MODE_NONE;
6558 
6559  /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6560 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6561  hi2c->ListenCpltCallback(hi2c);
6562 #else
6563  HAL_I2C_ListenCpltCallback(hi2c);
6564 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6565  }
6566 }
6567 
6577 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
6578 {
6579  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6580  uint32_t CurrentXferOptions = hi2c->XferOptions;
6581 
6582  /* Generate Start condition if first transfer */
6583  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
6584  {
6585  /* Generate Start */
6586  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6587  }
6588  else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
6589  {
6590  /* Generate ReStart */
6591  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6592  }
6593  else
6594  {
6595  /* Do nothing */
6596  }
6597 
6598  /* Wait until SB flag is set */
6599  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6600  {
6601  if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6602  {
6603  hi2c->ErrorCode = HAL_I2C_WRONG_START;
6604  }
6605  return HAL_TIMEOUT;
6606  }
6607 
6608  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
6609  {
6610  /* Send slave address */
6611  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6612  }
6613  else
6614  {
6615  /* Send header of slave address */
6616  hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
6617 
6618  /* Wait until ADD10 flag is set */
6619  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
6620  {
6621  return HAL_ERROR;
6622  }
6623 
6624  /* Send slave address */
6625  hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
6626  }
6627 
6628  /* Wait until ADDR flag is set */
6629  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6630  {
6631  return HAL_ERROR;
6632  }
6633 
6634  return HAL_OK;
6635 }
6636 
6647 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
6648 {
6649  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6650  uint32_t CurrentXferOptions = hi2c->XferOptions;
6651 
6652  /* Enable Acknowledge */
6653  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6654 
6655  /* Generate Start condition if first transfer */
6656  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
6657  {
6658  /* Generate Start */
6659  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6660  }
6661  else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
6662  {
6663  /* Generate ReStart */
6664  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6665  }
6666  else
6667  {
6668  /* Do nothing */
6669  }
6670 
6671  /* Wait until SB flag is set */
6672  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6673  {
6674  if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6675  {
6676  hi2c->ErrorCode = HAL_I2C_WRONG_START;
6677  }
6678  return HAL_TIMEOUT;
6679  }
6680 
6681  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
6682  {
6683  /* Send slave address */
6684  hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
6685  }
6686  else
6687  {
6688  /* Send header of slave address */
6689  hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
6690 
6691  /* Wait until ADD10 flag is set */
6692  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
6693  {
6694  return HAL_ERROR;
6695  }
6696 
6697  /* Send slave address */
6698  hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
6699 
6700  /* Wait until ADDR flag is set */
6701  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6702  {
6703  return HAL_ERROR;
6704  }
6705 
6706  /* Clear ADDR flag */
6707  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6708 
6709  /* Generate Restart */
6710  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6711 
6712  /* Wait until SB flag is set */
6713  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6714  {
6715  if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6716  {
6717  hi2c->ErrorCode = HAL_I2C_WRONG_START;
6718  }
6719  return HAL_TIMEOUT;
6720  }
6721 
6722  /* Send header of slave address */
6723  hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
6724  }
6725 
6726  /* Wait until ADDR flag is set */
6727  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6728  {
6729  return HAL_ERROR;
6730  }
6731 
6732  return HAL_OK;
6733 }
6734 
6747 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
6748 {
6749  /* Generate Start */
6750  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6751 
6752  /* Wait until SB flag is set */
6753  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6754  {
6755  if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6756  {
6757  hi2c->ErrorCode = HAL_I2C_WRONG_START;
6758  }
6759  return HAL_TIMEOUT;
6760  }
6761 
6762  /* Send slave address */
6763  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6764 
6765  /* Wait until ADDR flag is set */
6766  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6767  {
6768  return HAL_ERROR;
6769  }
6770 
6771  /* Clear ADDR flag */
6772  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6773 
6774  /* Wait until TXE flag is set */
6775  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6776  {
6777  if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6778  {
6779  /* Generate Stop */
6780  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6781  }
6782  return HAL_ERROR;
6783  }
6784 
6785  /* If Memory address size is 8Bit */
6786  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6787  {
6788  /* Send Memory Address */
6789  hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6790  }
6791  /* If Memory address size is 16Bit */
6792  else
6793  {
6794  /* Send MSB of Memory Address */
6795  hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
6796 
6797  /* Wait until TXE flag is set */
6798  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6799  {
6800  if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6801  {
6802  /* Generate Stop */
6803  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6804  }
6805  return HAL_ERROR;
6806  }
6807 
6808  /* Send LSB of Memory Address */
6809  hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6810  }
6811 
6812  return HAL_OK;
6813 }
6814 
6827 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
6828 {
6829  /* Enable Acknowledge */
6830  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6831 
6832  /* Generate Start */
6833  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6834 
6835  /* Wait until SB flag is set */
6836  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6837  {
6838  if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6839  {
6840  hi2c->ErrorCode = HAL_I2C_WRONG_START;
6841  }
6842  return HAL_TIMEOUT;
6843  }
6844 
6845  /* Send slave address */
6846  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6847 
6848  /* Wait until ADDR flag is set */
6849  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6850  {
6851  return HAL_ERROR;
6852  }
6853 
6854  /* Clear ADDR flag */
6855  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6856 
6857  /* Wait until TXE flag is set */
6858  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6859  {
6860  if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6861  {
6862  /* Generate Stop */
6863  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6864  }
6865  return HAL_ERROR;
6866  }
6867 
6868  /* If Memory address size is 8Bit */
6869  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6870  {
6871  /* Send Memory Address */
6872  hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6873  }
6874  /* If Memory address size is 16Bit */
6875  else
6876  {
6877  /* Send MSB of Memory Address */
6878  hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
6879 
6880  /* Wait until TXE flag is set */
6881  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6882  {
6883  if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6884  {
6885  /* Generate Stop */
6886  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6887  }
6888  return HAL_ERROR;
6889  }
6890 
6891  /* Send LSB of Memory Address */
6892  hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6893  }
6894 
6895  /* Wait until TXE flag is set */
6896  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6897  {
6898  if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6899  {
6900  /* Generate Stop */
6901  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6902  }
6903  return HAL_ERROR;
6904  }
6905 
6906  /* Generate Restart */
6907  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6908 
6909  /* Wait until SB flag is set */
6910  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6911  {
6912  if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6913  {
6914  hi2c->ErrorCode = HAL_I2C_WRONG_START;
6915  }
6916  return HAL_TIMEOUT;
6917  }
6918 
6919  /* Send slave address */
6920  hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
6921 
6922  /* Wait until ADDR flag is set */
6923  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6924  {
6925  return HAL_ERROR;
6926  }
6927 
6928  return HAL_OK;
6929 }
6930 
6936 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
6937 {
6938  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
6939 
6940  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6941  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6942  HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
6943  uint32_t CurrentXferOptions = hi2c->XferOptions;
6944 
6945  /* Disable EVT and ERR interrupt */
6946  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6947 
6948  /* Clear Complete callback */
6949  if (hi2c->hdmatx != NULL)
6950  {
6951  hi2c->hdmatx->XferCpltCallback = NULL;
6952  }
6953  if (hi2c->hdmarx != NULL)
6954  {
6955  hi2c->hdmarx->XferCpltCallback = NULL;
6956  }
6957 
6958  if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
6959  {
6960  /* Disable DMA Request */
6961  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6962 
6963  hi2c->XferCount = 0U;
6964 
6965  if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)
6966  {
6967  /* Set state at HAL_I2C_STATE_LISTEN */
6968  hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6969  hi2c->State = HAL_I2C_STATE_LISTEN;
6970 
6971  /* Call the corresponding callback to inform upper layer of End of Transfer */
6972 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6973  hi2c->SlaveTxCpltCallback(hi2c);
6974 #else
6975  HAL_I2C_SlaveTxCpltCallback(hi2c);
6976 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6977  }
6978  else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
6979  {
6980  /* Set state at HAL_I2C_STATE_LISTEN */
6981  hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6982  hi2c->State = HAL_I2C_STATE_LISTEN;
6983 
6984  /* Call the corresponding callback to inform upper layer of End of Transfer */
6985 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6986  hi2c->SlaveRxCpltCallback(hi2c);
6987 #else
6988  HAL_I2C_SlaveRxCpltCallback(hi2c);
6989 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6990  }
6991  else
6992  {
6993  /* Do nothing */
6994  }
6995 
6996  /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */
6997  __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6998  }
6999  /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */
7000  else if (hi2c->Mode != HAL_I2C_MODE_NONE)
7001  {
7002  if (hi2c->XferCount == (uint16_t)1)
7003  {
7004  /* Disable Acknowledge */
7005  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
7006  }
7007 
7008  /* Disable EVT and ERR interrupt */
7009  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
7010 
7011  /* Prepare next transfer or stop current transfer */
7012  if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
7013  {
7014  /* Generate Stop */
7015  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
7016  }
7017 
7018  /* Disable Last DMA */
7019  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
7020 
7021  /* Disable DMA Request */
7022  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
7023 
7024  hi2c->XferCount = 0U;
7025 
7026  /* Check if Errors has been detected during transfer */
7027  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
7028  {
7029 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7030  hi2c->ErrorCallback(hi2c);
7031 #else
7032  HAL_I2C_ErrorCallback(hi2c);
7033 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7034  }
7035  else
7036  {
7037  hi2c->State = HAL_I2C_STATE_READY;
7038 
7039  if (hi2c->Mode == HAL_I2C_MODE_MEM)
7040  {
7041  hi2c->Mode = HAL_I2C_MODE_NONE;
7042  hi2c->PreviousState = I2C_STATE_NONE;
7043 
7044 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7045  hi2c->MemRxCpltCallback(hi2c);
7046 #else
7047  HAL_I2C_MemRxCpltCallback(hi2c);
7048 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7049  }
7050  else
7051  {
7052  hi2c->Mode = HAL_I2C_MODE_NONE;
7053  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
7054  {
7055  hi2c->PreviousState = I2C_STATE_NONE;
7056  }
7057  else
7058  {
7059  hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
7060  }
7061 
7062 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7063  hi2c->MasterRxCpltCallback(hi2c);
7064 #else
7065  HAL_I2C_MasterRxCpltCallback(hi2c);
7066 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7067  }
7068  }
7069  }
7070  else
7071  {
7072  /* Do nothing */
7073  }
7074 }
7075 
7081 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
7082 {
7083  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
7084 
7085  /* Clear Complete callback */
7086  if (hi2c->hdmatx != NULL)
7087  {
7088  hi2c->hdmatx->XferCpltCallback = NULL;
7089  }
7090  if (hi2c->hdmarx != NULL)
7091  {
7092  hi2c->hdmarx->XferCpltCallback = NULL;
7093  }
7094 
7095  /* Ignore DMA FIFO error */
7096  if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
7097  {
7098  /* Disable Acknowledge */
7099  hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
7100 
7101  hi2c->XferCount = 0U;
7102 
7103  hi2c->State = HAL_I2C_STATE_READY;
7104  hi2c->Mode = HAL_I2C_MODE_NONE;
7105 
7106  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
7107 
7108 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7109  hi2c->ErrorCallback(hi2c);
7110 #else
7111  HAL_I2C_ErrorCallback(hi2c);
7112 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7113  }
7114 }
7115 
7122 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
7123 {
7124  __IO uint32_t count = 0U;
7125  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
7126 
7127  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
7128  HAL_I2C_StateTypeDef CurrentState = hi2c->State;
7129 
7130  /* During abort treatment, check that there is no pending STOP request */
7131  /* Wait until STOP flag is reset */
7132  count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
7133  do
7134  {
7135  if (count == 0U)
7136  {
7137  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7138  break;
7139  }
7140  count--;
7141  }
7142  while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
7143 
7144  /* Clear Complete callback */
7145  if (hi2c->hdmatx != NULL)
7146  {
7147  hi2c->hdmatx->XferCpltCallback = NULL;
7148  }
7149  if (hi2c->hdmarx != NULL)
7150  {
7151  hi2c->hdmarx->XferCpltCallback = NULL;
7152  }
7153 
7154  /* Disable Acknowledge */
7155  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
7156 
7157  hi2c->XferCount = 0U;
7158 
7159  /* Reset XferAbortCallback */
7160  if (hi2c->hdmatx != NULL)
7161  {
7162  hi2c->hdmatx->XferAbortCallback = NULL;
7163  }
7164  if (hi2c->hdmarx != NULL)
7165  {
7166  hi2c->hdmarx->XferAbortCallback = NULL;
7167  }
7168 
7169  /* Disable I2C peripheral to prevent dummy data in buffer */
7170  __HAL_I2C_DISABLE(hi2c);
7171 
7172  /* Check if come from abort from user */
7173  if (hi2c->State == HAL_I2C_STATE_ABORT)
7174  {
7175  hi2c->State = HAL_I2C_STATE_READY;
7176  hi2c->Mode = HAL_I2C_MODE_NONE;
7177  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
7178 
7179  /* Call the corresponding callback to inform upper layer of End of Transfer */
7180 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7181  hi2c->AbortCpltCallback(hi2c);
7182 #else
7183  HAL_I2C_AbortCpltCallback(hi2c);
7184 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7185  }
7186  else
7187  {
7188  if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
7189  {
7190  /* Renable I2C peripheral */
7191  __HAL_I2C_ENABLE(hi2c);
7192 
7193  /* Enable Acknowledge */
7194  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
7195 
7196  /* keep HAL_I2C_STATE_LISTEN */
7197  hi2c->PreviousState = I2C_STATE_NONE;
7198  hi2c->State = HAL_I2C_STATE_LISTEN;
7199  }
7200  else
7201  {
7202  hi2c->State = HAL_I2C_STATE_READY;
7203  hi2c->Mode = HAL_I2C_MODE_NONE;
7204  }
7205 
7206  /* Call the corresponding callback to inform upper layer of End of Transfer */
7207 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7208  hi2c->ErrorCallback(hi2c);
7209 #else
7210  HAL_I2C_ErrorCallback(hi2c);
7211 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7212  }
7213 }
7214 
7225 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
7226 {
7227  /* Wait until flag is set */
7228  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
7229  {
7230  /* Check for the Timeout */
7231  if (Timeout != HAL_MAX_DELAY)
7232  {
7233  if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7234  {
7235  if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
7236  {
7237  hi2c->PreviousState = I2C_STATE_NONE;
7238  hi2c->State = HAL_I2C_STATE_READY;
7239  hi2c->Mode = HAL_I2C_MODE_NONE;
7240  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7241 
7242  /* Process Unlocked */
7243  __HAL_UNLOCK(hi2c);
7244 
7245  return HAL_ERROR;
7246  }
7247  }
7248  }
7249  }
7250  return HAL_OK;
7251 }
7252 
7262 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
7263 {
7264  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
7265  {
7266  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7267  {
7268  /* Generate Stop */
7269  SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
7270 
7271  /* Clear AF Flag */
7272  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7273 
7274  hi2c->PreviousState = I2C_STATE_NONE;
7275  hi2c->State = HAL_I2C_STATE_READY;
7276  hi2c->Mode = HAL_I2C_MODE_NONE;
7277  hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
7278 
7279  /* Process Unlocked */
7280  __HAL_UNLOCK(hi2c);
7281 
7282  return HAL_ERROR;
7283  }
7284 
7285  /* Check for the Timeout */
7286  if (Timeout != HAL_MAX_DELAY)
7287  {
7288  if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7289  {
7290  if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET))
7291  {
7292  hi2c->PreviousState = I2C_STATE_NONE;
7293  hi2c->State = HAL_I2C_STATE_READY;
7294  hi2c->Mode = HAL_I2C_MODE_NONE;
7295  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7296 
7297  /* Process Unlocked */
7298  __HAL_UNLOCK(hi2c);
7299 
7300  return HAL_ERROR;
7301  }
7302  }
7303  }
7304  }
7305  return HAL_OK;
7306 }
7307 
7316 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7317 {
7318  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
7319  {
7320  /* Check if a NACK is detected */
7321  if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7322  {
7323  return HAL_ERROR;
7324  }
7325 
7326  /* Check for the Timeout */
7327  if (Timeout != HAL_MAX_DELAY)
7328  {
7329  if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7330  {
7331  if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET))
7332  {
7333  hi2c->PreviousState = I2C_STATE_NONE;
7334  hi2c->State = HAL_I2C_STATE_READY;
7335  hi2c->Mode = HAL_I2C_MODE_NONE;
7336  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7337 
7338  /* Process Unlocked */
7339  __HAL_UNLOCK(hi2c);
7340 
7341  return HAL_ERROR;
7342  }
7343  }
7344  }
7345  }
7346  return HAL_OK;
7347 }
7348 
7357 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7358 {
7359  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
7360  {
7361  /* Check if a NACK is detected */
7362  if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7363  {
7364  return HAL_ERROR;
7365  }
7366 
7367  /* Check for the Timeout */
7368  if (Timeout != HAL_MAX_DELAY)
7369  {
7370  if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7371  {
7372  if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET))
7373  {
7374  hi2c->PreviousState = I2C_STATE_NONE;
7375  hi2c->State = HAL_I2C_STATE_READY;
7376  hi2c->Mode = HAL_I2C_MODE_NONE;
7377  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7378 
7379  /* Process Unlocked */
7380  __HAL_UNLOCK(hi2c);
7381 
7382  return HAL_ERROR;
7383  }
7384  }
7385  }
7386  }
7387  return HAL_OK;
7388 }
7389 
7398 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7399 {
7400  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7401  {
7402  /* Check if a NACK is detected */
7403  if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7404  {
7405  return HAL_ERROR;
7406  }
7407 
7408  /* Check for the Timeout */
7409  if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7410  {
7411  if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
7412  {
7413  hi2c->PreviousState = I2C_STATE_NONE;
7414  hi2c->State = HAL_I2C_STATE_READY;
7415  hi2c->Mode = HAL_I2C_MODE_NONE;
7416  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7417 
7418  /* Process Unlocked */
7419  __HAL_UNLOCK(hi2c);
7420 
7421  return HAL_ERROR;
7422  }
7423  }
7424  }
7425  return HAL_OK;
7426 }
7427 
7434 static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c)
7435 {
7436  __IO uint32_t count = 0U;
7437 
7438  /* Wait until STOP flag is reset */
7439  count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U);
7440  do
7441  {
7442  count--;
7443  if (count == 0U)
7444  {
7445  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7446 
7447  return HAL_ERROR;
7448  }
7449  }
7450  while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
7451 
7452  return HAL_OK;
7453 }
7454 
7463 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7464 {
7465 
7466  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
7467  {
7468  /* Check if a STOPF is detected */
7469  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
7470  {
7471  /* Clear STOP Flag */
7472  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7473 
7474  hi2c->PreviousState = I2C_STATE_NONE;
7475  hi2c->State = HAL_I2C_STATE_READY;
7476  hi2c->Mode = HAL_I2C_MODE_NONE;
7477  hi2c->ErrorCode |= HAL_I2C_ERROR_NONE;
7478 
7479  /* Process Unlocked */
7480  __HAL_UNLOCK(hi2c);
7481 
7482  return HAL_ERROR;
7483  }
7484 
7485  /* Check for the Timeout */
7486  if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7487  {
7488  if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
7489  {
7490  hi2c->PreviousState = I2C_STATE_NONE;
7491  hi2c->State = HAL_I2C_STATE_READY;
7492  hi2c->Mode = HAL_I2C_MODE_NONE;
7493  hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7494 
7495  /* Process Unlocked */
7496  __HAL_UNLOCK(hi2c);
7497 
7498  return HAL_ERROR;
7499  }
7500  }
7501  }
7502  return HAL_OK;
7503 }
7504 
7511 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
7512 {
7513  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7514  {
7515  /* Clear NACKF Flag */
7516  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7517 
7518  hi2c->PreviousState = I2C_STATE_NONE;
7519  hi2c->State = HAL_I2C_STATE_READY;
7520  hi2c->Mode = HAL_I2C_MODE_NONE;
7521  hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
7522 
7523  /* Process Unlocked */
7524  __HAL_UNLOCK(hi2c);
7525 
7526  return HAL_ERROR;
7527  }
7528  return HAL_OK;
7529 }
7530 
7536 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7537 {
7538  /* if user set XferOptions to I2C_OTHER_FRAME */
7539  /* it request implicitly to generate a restart condition */
7540  /* set XferOptions to I2C_FIRST_FRAME */
7541  if (hi2c->XferOptions == I2C_OTHER_FRAME)
7542  {
7543  hi2c->XferOptions = I2C_FIRST_FRAME;
7544  }
7545  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7546  /* it request implicitly to generate a restart condition */
7547  /* then generate a stop condition at the end of transfer */
7548  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7549  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7550  {
7551  hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7552  }
7553  else
7554  {
7555  /* Nothing to do */
7556  }
7557 }
7558 
7563 #endif /* HAL_I2C_MODULE_ENABLED */
HAL_DMA_Abort_IT
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
Aborts the DMA Transfer in Interrupt mode.
Definition: stm32f4xx_hal_dma.c:580
HAL_DMA_Start_IT
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
Start the DMA Transfer with interrupt enabled.
Definition: stm32f4xx_hal_dma.c:451
HAL_DMA_GetError
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
Return the DMA error code.
Definition: stm32f4xx_hal_dma.c:1125
HAL_DMA_GetState
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
Returns the DMA state.
Definition: stm32f4xx_hal_dma.c:1114
HAL_GetTick
uint32_t HAL_GetTick(void)
Provides a tick value in millisecond.
Definition: stm32f4xx_hal.c:323
HAL_I2C_ModeTypeDef
HAL_I2C_ModeTypeDef
Definition: stm32f4xx_hal_i2c.h:147
HAL_I2C_MODE_MASTER
@ HAL_I2C_MODE_MASTER
Definition: stm32f4xx_hal_i2c.h:149
HAL_I2C_MODE_MEM
@ HAL_I2C_MODE_MEM
Definition: stm32f4xx_hal_i2c.h:151
HAL_I2C_MODE_SLAVE
@ HAL_I2C_MODE_SLAVE
Definition: stm32f4xx_hal_i2c.h:150
HAL_I2C_MODE_NONE
@ HAL_I2C_MODE_NONE
Definition: stm32f4xx_hal_i2c.h:148
HAL_I2C_StateTypeDef
HAL_I2C_StateTypeDef
Definition: stm32f4xx_hal_i2c.h:107
HAL_I2C_STATE_BUSY
@ HAL_I2C_STATE_BUSY
Definition: stm32f4xx_hal_i2c.h:110
HAL_I2C_STATE_LISTEN
@ HAL_I2C_STATE_LISTEN
Definition: stm32f4xx_hal_i2c.h:113
HAL_I2C_STATE_BUSY_TX_LISTEN
@ HAL_I2C_STATE_BUSY_TX_LISTEN
Definition: stm32f4xx_hal_i2c.h:114
HAL_I2C_STATE_ABORT
@ HAL_I2C_STATE_ABORT
Definition: stm32f4xx_hal_i2c.h:118
HAL_I2C_STATE_TIMEOUT
@ HAL_I2C_STATE_TIMEOUT
Definition: stm32f4xx_hal_i2c.h:119
HAL_I2C_STATE_BUSY_RX
@ HAL_I2C_STATE_BUSY_RX
Definition: stm32f4xx_hal_i2c.h:112
HAL_I2C_STATE_BUSY_RX_LISTEN
@ HAL_I2C_STATE_BUSY_RX_LISTEN
Definition: stm32f4xx_hal_i2c.h:116
HAL_I2C_STATE_RESET
@ HAL_I2C_STATE_RESET
Definition: stm32f4xx_hal_i2c.h:108
HAL_I2C_STATE_BUSY_TX
@ HAL_I2C_STATE_BUSY_TX
Definition: stm32f4xx_hal_i2c.h:111
HAL_I2C_STATE_READY
@ HAL_I2C_STATE_READY
Definition: stm32f4xx_hal_i2c.h:109
HAL_I2C_RegisterCallback
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
Register a User I2C Callback To be used instead of the weak predefined callback.
Definition: stm32f4xx_hal_i2c.c:654
HAL_I2C_MspDeInit
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
DeInitialize the I2C MSP.
Definition: stm32f4xx_hal_i2c.c:622
HAL_I2C_MspInit
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
Initialize the I2C MSP.
Definition: stm32f4xx_hal_i2c.c:606
HAL_I2C_UnRegisterCallback
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
Unregister an I2C Callback I2C callback is redirected to the weak predefined callback.
Definition: stm32f4xx_hal_i2c.c:781
HAL_I2C_RegisterAddrCallback
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
Register the Slave Address Match I2C Callback To be used instead of the weak HAL_I2C_AddrCallback() p...
Definition: stm32f4xx_hal_i2c.c:888
HAL_I2C_UnRegisterAddrCallback
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
UnRegister the Slave Address Match I2C Callback Info Ready I2C Callback is redirected to the weak HAL...
Definition: stm32f4xx_hal_i2c.c:927
HAL_I2C_Init
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
Initializes the I2C according to the specified parameters in the I2C_InitTypeDef and initialize the a...
Definition: stm32f4xx_hal_i2c.c:445
HAL_I2C_DeInit
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
DeInitialize the I2C peripheral.
Definition: stm32f4xx_hal_i2c.c:560
HAL_I2C_Master_Seq_Receive_IT
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt.
Definition: stm32f4xx_hal_i2c.c:3843
HAL_I2C_Slave_Seq_Transmit_DMA
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave mode an amount of data in non-blocking mode with DMA.
Definition: stm32f4xx_hal_i2c.c:4245
HAL_I2C_Mem_Write_DMA
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
Definition: stm32f4xx_hal_i2c.c:3054
HAL_I2C_Slave_Seq_Receive_IT
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt.
Definition: stm32f4xx_hal_i2c.c:4419
HAL_I2C_Mem_Read_IT
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address.
Definition: stm32f4xx_hal_i2c.c:2963
HAL_I2C_Master_Receive_DMA
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with DMA.
Definition: stm32f4xx_hal_i2c.c:2117
HAL_I2C_Master_Receive_IT
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
Definition: stm32f4xx_hal_i2c.c:1756
HAL_I2C_Mem_Write
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Write an amount of data in blocking mode to a specific memory address.
Definition: stm32f4xx_hal_i2c.c:2503
HAL_I2C_Slave_Receive_IT
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
Definition: stm32f4xx_hal_i2c.c:1898
HAL_I2C_Master_Transmit_IT
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
Definition: stm32f4xx_hal_i2c.c:1679
HAL_I2C_Slave_Transmit_DMA
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
Definition: stm32f4xx_hal_i2c.c:2270
HAL_I2C_Master_Seq_Transmit_IT
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
Definition: stm32f4xx_hal_i2c.c:3568
HAL_I2C_Master_Receive
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receives in master mode an amount of data in blocking mode.
Definition: stm32f4xx_hal_i2c.c:1177
HAL_I2C_Slave_Seq_Transmit_IT
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt.
Definition: stm32f4xx_hal_i2c.c:4179
HAL_I2C_Mem_Read
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Read an amount of data in blocking mode from a specific memory address.
Definition: stm32f4xx_hal_i2c.c:2626
HAL_I2C_Master_Seq_Receive_DMA
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in master mode an amount of data in non-blocking mode with DMA.
Definition: stm32f4xx_hal_i2c.c:3964
HAL_I2C_Slave_Transmit
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in slave mode an amount of data in blocking mode.
Definition: stm32f4xx_hal_i2c.c:1428
HAL_I2C_Slave_Receive
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Receive in slave mode an amount of data in blocking mode.
Definition: stm32f4xx_hal_i2c.c:1558
HAL_I2C_Master_Transmit
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
Transmits in master mode an amount of data in blocking mode.
Definition: stm32f4xx_hal_i2c.c:1056
HAL_I2C_Master_Transmit_DMA
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
Transmit in master mode an amount of data in non-blocking mode with DMA.
Definition: stm32f4xx_hal_i2c.c:1962
HAL_I2C_Mem_Read_DMA
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
Definition: stm32f4xx_hal_i2c.c:3236
HAL_I2C_Mem_Write_IT
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
Definition: stm32f4xx_hal_i2c.c:2878
HAL_I2C_Slave_Transmit_IT
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
Definition: stm32f4xx_hal_i2c.c:1836
HAL_I2C_Master_Seq_Transmit_DMA
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
Definition: stm32f4xx_hal_i2c.c:3663
HAL_I2C_Master_Abort_IT
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
Abort a master or memory I2C IT or DMA process communication with Interrupt.
Definition: stm32f4xx_hal_i2c.c:4723
HAL_I2C_EnableListen_IT
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
Enable the Address listen mode with Interrupt.
Definition: stm32f4xx_hal_i2c.c:4655
HAL_I2C_Slave_Receive_DMA
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
Receive in slave mode an amount of data in non-blocking mode with DMA.
Definition: stm32f4xx_hal_i2c.c:2384
HAL_I2C_IsDeviceReady
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
Checks if target device is ready for communication.
Definition: stm32f4xx_hal_i2c.c:3432
HAL_I2C_Slave_Seq_Receive_DMA
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
Sequential receive in slave mode an amount of data in non-blocking mode with DMA.
Definition: stm32f4xx_hal_i2c.c:4485
HAL_I2C_DisableListen_IT
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
Disable the Address listen mode with Interrupt.
Definition: stm32f4xx_hal_i2c.c:4688
HAL_I2C_GetMode
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
Returns the I2C Master, Slave, Memory or no mode.
Definition: stm32f4xx_hal_i2c.c:5226
HAL_I2C_GetError
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
Return the I2C error code.
Definition: stm32f4xx_hal_i2c.c:5237
HAL_I2C_GetState
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
Return the I2C handle state.
Definition: stm32f4xx_hal_i2c.c:5214
HAL_I2C_EV_IRQHandler
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
This function handles I2C event interrupt request.
Definition: stm32f4xx_hal_i2c.c:4783
HAL_I2C_MasterRxCpltCallback
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
Master Rx Transfer completed callback.
Definition: stm32f4xx_hal_i2c.c:5048
HAL_I2C_MemTxCpltCallback
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
Memory Tx Transfer completed callback.
Definition: stm32f4xx_hal_i2c.c:5131
HAL_I2C_AbortCpltCallback
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
I2C abort callback.
Definition: stm32f4xx_hal_i2c.c:5179
HAL_I2C_ErrorCallback
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
I2C error callback.
Definition: stm32f4xx_hal_i2c.c:5163
HAL_I2C_MemRxCpltCallback
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
Memory Rx Transfer completed callback.
Definition: stm32f4xx_hal_i2c.c:5147
HAL_I2C_ListenCpltCallback
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
Listen Complete callback.
Definition: stm32f4xx_hal_i2c.c:5115
HAL_I2C_SlaveRxCpltCallback
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
Slave Rx Transfer completed callback.
Definition: stm32f4xx_hal_i2c.c:5079
HAL_I2C_AddrCallback
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Slave Address Match callback.
Definition: stm32f4xx_hal_i2c.c:5097
HAL_I2C_MasterTxCpltCallback
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
Master Tx Transfer completed callback.
Definition: stm32f4xx_hal_i2c.c:5032
HAL_I2C_ER_IRQHandler
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
This function handles I2C error interrupt request.
Definition: stm32f4xx_hal_i2c.c:4952
HAL_I2C_SlaveTxCpltCallback
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
Slave Tx Transfer completed callback.
Definition: stm32f4xx_hal_i2c.c:5063
pI2C_CallbackTypeDef
void(* pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c)
HAL I2C Callback pointer definition.
Definition: stm32f4xx_hal_i2c.h:269
pI2C_AddrCallbackTypeDef
void(* pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
Definition: stm32f4xx_hal_i2c.h:270
HAL_I2C_CallbackIDTypeDef
HAL_I2C_CallbackIDTypeDef
HAL I2C Callback ID enumeration definition.
Definition: stm32f4xx_hal_i2c.h:250
HAL_I2C_MASTER_TX_COMPLETE_CB_ID
@ HAL_I2C_MASTER_TX_COMPLETE_CB_ID
Definition: stm32f4xx_hal_i2c.h:251
HAL_I2C_MSPINIT_CB_ID
@ HAL_I2C_MSPINIT_CB_ID
Definition: stm32f4xx_hal_i2c.h:261
HAL_I2C_MEM_RX_COMPLETE_CB_ID
@ HAL_I2C_MEM_RX_COMPLETE_CB_ID
Definition: stm32f4xx_hal_i2c.h:257
HAL_I2C_MASTER_RX_COMPLETE_CB_ID
@ HAL_I2C_MASTER_RX_COMPLETE_CB_ID
Definition: stm32f4xx_hal_i2c.h:252
HAL_I2C_MSPDEINIT_CB_ID
@ HAL_I2C_MSPDEINIT_CB_ID
Definition: stm32f4xx_hal_i2c.h:262
HAL_I2C_ERROR_CB_ID
@ HAL_I2C_ERROR_CB_ID
Definition: stm32f4xx_hal_i2c.h:258
HAL_I2C_LISTEN_COMPLETE_CB_ID
@ HAL_I2C_LISTEN_COMPLETE_CB_ID
Definition: stm32f4xx_hal_i2c.h:255
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID
@ HAL_I2C_SLAVE_TX_COMPLETE_CB_ID
Definition: stm32f4xx_hal_i2c.h:253
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID
@ HAL_I2C_SLAVE_RX_COMPLETE_CB_ID
Definition: stm32f4xx_hal_i2c.h:254
HAL_I2C_ABORT_CB_ID
@ HAL_I2C_ABORT_CB_ID
Definition: stm32f4xx_hal_i2c.h:259
HAL_I2C_MEM_TX_COMPLETE_CB_ID
@ HAL_I2C_MEM_TX_COMPLETE_CB_ID
Definition: stm32f4xx_hal_i2c.h:256
HAL_RCC_GetPCLK1Freq
uint32_t HAL_RCC_GetPCLK1Freq(void)
Returns the PCLK1 frequency.
Definition: stm32f4xx_hal_rcc.c:954
stm32f4xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
HAL_DMA_STATE_READY
@ HAL_DMA_STATE_READY
Definition: stm32f4xx_hal_dma.h:105
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f4xx_hal_dma.h:139