PLLSAI

Collaboration diagram for PLLSAI:

Functions
__STATIC_INLINE void	LL_RCC_PLLSAI_Enable (void)
	Enable PLLSAI @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable. More...
__STATIC_INLINE void	LL_RCC_PLLSAI_Disable (void)
	Disable PLLSAI @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI_IsReady (void)
	Check if PLLSAI Ready @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady. More...
__STATIC_INLINE void	LL_RCC_PLLSAI_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
	Configure PLLSAI used for SAI domain clock. More...
__STATIC_INLINE void	LL_RCC_PLLSAI_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
	Configure PLLSAI used for 48Mhz domain clock. More...
__STATIC_INLINE void	LL_RCC_PLLSAI_ConfigDomain_LTDC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
	Configure PLLSAI used for LTDC domain clock. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI_GetDivider (void)
	Get division factor for PLLSAI input clock @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI_GetN (void)
	Get SAIPLL multiplication factor for VCO @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI_GetQ (void)
	Get SAIPLL division factor for PLLSAIQ @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI_GetR (void)
	Get SAIPLL division factor for PLLSAIR. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI_GetP (void)
	Get SAIPLL division factor for PLLSAIP. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI_GetDIVQ (void)
	Get SAIPLL division factor for PLLSAIDIVQ. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLSAI_GetDIVR (void)
	Get SAIPLL division factor for PLLSAIDIVR. More...

Detailed Description

Function Documentation

LL_RCC_PLLSAI_ConfigDomain_48M()

__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLP
	)

Configure PLLSAI used for 48Mhz domain clock.

Note

PLL Source and PLLM Divider can be written only when PLL, PLLI2S and PLLSAI(*) are disabled

PLLN/PLLP can be written only when PLLSAI is disabled

This can be selected for USB, RNG, SDIO @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M
PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M
PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M
PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M
PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLSAIM_DIV_63
PLLN	Between 50 and 432
PLLP	This parameter can be one of the following values: LL_RCC_PLLSAIP_DIV_2 LL_RCC_PLLSAIP_DIV_4 LL_RCC_PLLSAIP_DIV_6 LL_RCC_PLLSAIP_DIV_8

Return values

None

Definition at line 6207 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLSAI_ConfigDomain_LTDC()

__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLR,
		uint32_t	PLLDIVR
	)

Configure PLLSAI used for LTDC domain clock.

Note

PLL Source and PLLM Divider can be written only when PLL, PLLI2S and PLLSAI(*) are disabled

PLLN/PLLR can be written only when PLLSAI is disabled

This can be selected for LTDC @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC
PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC
PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC
PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC
DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLSAIM_DIV_63
PLLN	Between 49/50(*) and 432 (*) value not defined in all devices.
PLLR	This parameter can be one of the following values: LL_RCC_PLLSAIR_DIV_2 LL_RCC_PLLSAIR_DIV_3 LL_RCC_PLLSAIR_DIV_4 LL_RCC_PLLSAIR_DIV_5 LL_RCC_PLLSAIR_DIV_6 LL_RCC_PLLSAIR_DIV_7
PLLDIVR	This parameter can be one of the following values: LL_RCC_PLLSAIDIVR_DIV_2 LL_RCC_PLLSAIDIVR_DIV_4 LL_RCC_PLLSAIDIVR_DIV_8 LL_RCC_PLLSAIDIVR_DIV_16

Return values

None

Definition at line 6314 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLSAI_ConfigDomain_SAI()

__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLQ,
		uint32_t	PLLDIVQ
	)

Configure PLLSAI used for SAI domain clock.

Note

PLL Source and PLLM Divider can be written only when PLL, PLLI2S and PLLSAI(*) are disabled

PLLN/PLLQ can be written only when PLLSAI is disabled

This can be selected for SAI @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI
PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI
PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI
PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI
DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLSAIM_DIV_63
PLLN	Between 49/50(*) and 432 (*) value not defined in all devices.
PLLQ	This parameter can be one of the following values: LL_RCC_PLLSAIQ_DIV_2 LL_RCC_PLLSAIQ_DIV_3 LL_RCC_PLLSAIQ_DIV_4 LL_RCC_PLLSAIQ_DIV_5 LL_RCC_PLLSAIQ_DIV_6 LL_RCC_PLLSAIQ_DIV_7 LL_RCC_PLLSAIQ_DIV_8 LL_RCC_PLLSAIQ_DIV_9 LL_RCC_PLLSAIQ_DIV_10 LL_RCC_PLLSAIQ_DIV_11 LL_RCC_PLLSAIQ_DIV_12 LL_RCC_PLLSAIQ_DIV_13 LL_RCC_PLLSAIQ_DIV_14 LL_RCC_PLLSAIQ_DIV_15
PLLDIVQ	This parameter can be one of the following values: LL_RCC_PLLSAIDIVQ_DIV_1 LL_RCC_PLLSAIDIVQ_DIV_2 LL_RCC_PLLSAIDIVQ_DIV_3 LL_RCC_PLLSAIDIVQ_DIV_4 LL_RCC_PLLSAIDIVQ_DIV_5 LL_RCC_PLLSAIDIVQ_DIV_6 LL_RCC_PLLSAIDIVQ_DIV_7 LL_RCC_PLLSAIDIVQ_DIV_8 LL_RCC_PLLSAIDIVQ_DIV_9 LL_RCC_PLLSAIDIVQ_DIV_10 LL_RCC_PLLSAIDIVQ_DIV_11 LL_RCC_PLLSAIDIVQ_DIV_12 LL_RCC_PLLSAIDIVQ_DIV_13 LL_RCC_PLLSAIDIVQ_DIV_14 LL_RCC_PLLSAIDIVQ_DIV_15 LL_RCC_PLLSAIDIVQ_DIV_16 LL_RCC_PLLSAIDIVQ_DIV_17 LL_RCC_PLLSAIDIVQ_DIV_18 LL_RCC_PLLSAIDIVQ_DIV_19 LL_RCC_PLLSAIDIVQ_DIV_20 LL_RCC_PLLSAIDIVQ_DIV_21 LL_RCC_PLLSAIDIVQ_DIV_22 LL_RCC_PLLSAIDIVQ_DIV_23 LL_RCC_PLLSAIDIVQ_DIV_24 LL_RCC_PLLSAIDIVQ_DIV_25 LL_RCC_PLLSAIDIVQ_DIV_26 LL_RCC_PLLSAIDIVQ_DIV_27 LL_RCC_PLLSAIDIVQ_DIV_28 LL_RCC_PLLSAIDIVQ_DIV_29 LL_RCC_PLLSAIDIVQ_DIV_30 LL_RCC_PLLSAIDIVQ_DIV_31 LL_RCC_PLLSAIDIVQ_DIV_32

Return values

None

Definition at line 6108 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLSAI_Disable()

__STATIC_INLINE void LL_RCC_PLLSAI_Disable

(

void

)

Disable PLLSAI @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable.

Return values

None

Definition at line 5962 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLSAI_Enable()

__STATIC_INLINE void LL_RCC_PLLSAI_Enable

(

void

)

Enable PLLSAI @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable.

Return values

None

Definition at line 5952 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLSAI_GetDivider()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider

(

void

)

Get division factor for PLLSAI input clock @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider
PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider.

Return values

Returned

value can be one of the following values: LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLSAIM_DIV_63

Definition at line 6391 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLSAI_GetDIVQ()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ

(

void

)

Get SAIPLL division factor for PLLSAIDIVQ.

Note

used PLLSAICLK selected (SAI clock) @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ

Return values

Returned

value can be one of the following values: LL_RCC_PLLSAIDIVQ_DIV_1 LL_RCC_PLLSAIDIVQ_DIV_2 LL_RCC_PLLSAIDIVQ_DIV_3 LL_RCC_PLLSAIDIVQ_DIV_4 LL_RCC_PLLSAIDIVQ_DIV_5 LL_RCC_PLLSAIDIVQ_DIV_6 LL_RCC_PLLSAIDIVQ_DIV_7 LL_RCC_PLLSAIDIVQ_DIV_8 LL_RCC_PLLSAIDIVQ_DIV_9 LL_RCC_PLLSAIDIVQ_DIV_10 LL_RCC_PLLSAIDIVQ_DIV_11 LL_RCC_PLLSAIDIVQ_DIV_12 LL_RCC_PLLSAIDIVQ_DIV_13 LL_RCC_PLLSAIDIVQ_DIV_14 LL_RCC_PLLSAIDIVQ_DIV_15 LL_RCC_PLLSAIDIVQ_DIV_16 LL_RCC_PLLSAIDIVQ_DIV_17 LL_RCC_PLLSAIDIVQ_DIV_18 LL_RCC_PLLSAIDIVQ_DIV_19 LL_RCC_PLLSAIDIVQ_DIV_20 LL_RCC_PLLSAIDIVQ_DIV_21 LL_RCC_PLLSAIDIVQ_DIV_22 LL_RCC_PLLSAIDIVQ_DIV_23 LL_RCC_PLLSAIDIVQ_DIV_24 LL_RCC_PLLSAIDIVQ_DIV_25 LL_RCC_PLLSAIDIVQ_DIV_26 LL_RCC_PLLSAIDIVQ_DIV_27 LL_RCC_PLLSAIDIVQ_DIV_28 LL_RCC_PLLSAIDIVQ_DIV_29 LL_RCC_PLLSAIDIVQ_DIV_30 LL_RCC_PLLSAIDIVQ_DIV_31 LL_RCC_PLLSAIDIVQ_DIV_32

Definition at line 6510 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLSAI_GetDIVR()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR

(

void

)

Get SAIPLL division factor for PLLSAIDIVR.

Note

used for LTDC domain clock @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR

Return values

Returned

value can be one of the following values: LL_RCC_PLLSAIDIVR_DIV_2 LL_RCC_PLLSAIDIVR_DIV_4 LL_RCC_PLLSAIDIVR_DIV_8 LL_RCC_PLLSAIDIVR_DIV_16

Definition at line 6526 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLSAI_GetN()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN

(

void

)

Get SAIPLL multiplication factor for VCO @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN.

Return values

Between

49/50(*) and 432 (*) value not defined in all devices.

Definition at line 6407 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLSAI_GetP()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP

(

void

)

Get SAIPLL division factor for PLLSAIP.

Note

used for PLL48MCLK (48M domain clock) @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP

Return values

Returned

value can be one of the following values: LL_RCC_PLLSAIP_DIV_2 LL_RCC_PLLSAIP_DIV_4 LL_RCC_PLLSAIP_DIV_6 LL_RCC_PLLSAIP_DIV_8

Definition at line 6466 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLSAI_GetQ()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ

(

void

)

Get SAIPLL division factor for PLLSAIQ @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ.

Return values

Returned

value can be one of the following values: LL_RCC_PLLSAIQ_DIV_2 LL_RCC_PLLSAIQ_DIV_3 LL_RCC_PLLSAIQ_DIV_4 LL_RCC_PLLSAIQ_DIV_5 LL_RCC_PLLSAIQ_DIV_6 LL_RCC_PLLSAIQ_DIV_7 LL_RCC_PLLSAIQ_DIV_8 LL_RCC_PLLSAIQ_DIV_9 LL_RCC_PLLSAIQ_DIV_10 LL_RCC_PLLSAIQ_DIV_11 LL_RCC_PLLSAIQ_DIV_12 LL_RCC_PLLSAIQ_DIV_13 LL_RCC_PLLSAIQ_DIV_14 LL_RCC_PLLSAIQ_DIV_15

Definition at line 6431 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLSAI_GetR()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR

(

void

)

Get SAIPLL division factor for PLLSAIR.

Note

used for PLLSAICLK (SAI clock) @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR

Return values

Returned

value can be one of the following values: LL_RCC_PLLSAIR_DIV_2 LL_RCC_PLLSAIR_DIV_3 LL_RCC_PLLSAIR_DIV_4 LL_RCC_PLLSAIR_DIV_5 LL_RCC_PLLSAIR_DIV_6 LL_RCC_PLLSAIR_DIV_7

Definition at line 6449 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLSAI_IsReady()

__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady

(

void

)

Check if PLLSAI Ready @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady.

Return values

State

of bit (1 or 0).

Definition at line 5972 of file stm32f4xx_ll_rcc.h.