PLLI2S

Collaboration diagram for PLLI2S:

Functions
__STATIC_INLINE void	LL_RCC_PLLI2S_Enable (void)
	Enable PLLI2S @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable. More...
__STATIC_INLINE void	LL_RCC_PLLI2S_Disable (void)
	Disable PLLI2S @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLI2S_IsReady (void)
	Check if PLLI2S Ready @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady. More...
__STATIC_INLINE void	LL_RCC_PLLI2S_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
	Configure PLLI2S used for SAI domain clock. More...
__STATIC_INLINE void	LL_RCC_PLLI2S_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
	Configure PLLI2S used for 48Mhz domain clock. More...
__STATIC_INLINE void	LL_RCC_PLLI2S_ConfigDomain_SPDIFRX (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
	Configure PLLI2S used for SPDIFRX domain clock. More...
__STATIC_INLINE void	LL_RCC_PLLI2S_ConfigDomain_I2S (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
	Configure PLLI2S used for I2S1 domain clock. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLI2S_GetN (void)
	Get I2SPLL multiplication factor for VCO @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLI2S_GetQ (void)
	Get I2SPLL division factor for PLLI2SQ @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLI2S_GetR (void)
	Get I2SPLL division factor for PLLI2SR. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLI2S_GetP (void)
	Get I2SPLL division factor for PLLI2SP. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLI2S_GetDIVQ (void)
	Get I2SPLL division factor for PLLI2SDIVQ. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLI2S_GetDIVR (void)
	Get I2SPLL division factor for PLLI2SDIVR. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLI2S_GetDivider (void)
	Get division factor for PLLI2S input clock @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider. More...
__STATIC_INLINE uint32_t	LL_RCC_PLLI2S_GetMainSource (void)
	Get the oscillator used as PLL clock source. @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource. More...

Detailed Description

Function Documentation

LL_RCC_PLLI2S_ConfigDomain_48M()

__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLQ
	)

Configure PLLI2S used for 48Mhz domain clock.

Note

PLL Source and PLLM Divider can be written only when PLL, PLLI2S and PLLSAI(*) are disabled

PLLN/PLLQ can be written only when PLLI2S is disabled

This can be selected for RNG, USB, SDIO @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M
PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M
PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M
PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M
PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M
PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE LL_RCC_PLLI2SSOURCE_PIN (*) (*) value not defined in all devices.
PLLM	This parameter can be one of the following values: LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLI2SM_DIV_63
PLLN	Between 50 and 432
PLLQ	This parameter can be one of the following values: LL_RCC_PLLI2SQ_DIV_2 LL_RCC_PLLI2SQ_DIV_3 LL_RCC_PLLI2SQ_DIV_4 LL_RCC_PLLI2SQ_DIV_5 LL_RCC_PLLI2SQ_DIV_6 LL_RCC_PLLI2SQ_DIV_7 LL_RCC_PLLI2SQ_DIV_8 LL_RCC_PLLI2SQ_DIV_9 LL_RCC_PLLI2SQ_DIV_10 LL_RCC_PLLI2SQ_DIV_11 LL_RCC_PLLI2SQ_DIV_12 LL_RCC_PLLI2SQ_DIV_13 LL_RCC_PLLI2SQ_DIV_14 LL_RCC_PLLI2SQ_DIV_15

Return values

None

Definition at line 5460 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLI2S_ConfigDomain_I2S()

__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLR
	)

Configure PLLI2S used for I2S1 domain clock.

Note

PLL Source and PLLM Divider can be written only when PLL, PLLI2S and PLLSAI(*) are disabled

PLLN/PLLR can be written only when PLLI2S is disabled

This can be selected for I2S @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S
PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S
PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S
PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S
PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S
PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE LL_RCC_PLLI2SSOURCE_PIN (*) (*) value not defined in all devices.
PLLM	This parameter can be one of the following values: LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLI2SM_DIV_63
PLLN	Between 50/192(*) and 432 (*) value not defined in all devices.
PLLR	This parameter can be one of the following values: LL_RCC_PLLI2SR_DIV_2 LL_RCC_PLLI2SR_DIV_3 LL_RCC_PLLI2SR_DIV_4 LL_RCC_PLLI2SR_DIV_5 LL_RCC_PLLI2SR_DIV_6 LL_RCC_PLLI2SR_DIV_7

Return values

None

Definition at line 5664 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLI2S_ConfigDomain_SAI()

__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLQ_R,
		uint32_t	PLLDIVQ_R
	)

Configure PLLI2S used for SAI domain clock.

Note

PLL Source and PLLM Divider can be written only when PLL, PLLI2S and PLLSAI(*) are disabled

PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled

This can be selected for SAI @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI
PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI
PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI
PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI
PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI
PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI
PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI
DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI
DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE LL_RCC_PLLI2SSOURCE_PIN (*) (*) value not defined in all devices.
PLLM	This parameter can be one of the following values: LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLI2SM_DIV_63
PLLN	Between 50/192(*) and 432 (*) value not defined in all devices.
PLLQ_R	This parameter can be one of the following values: LL_RCC_PLLI2SQ_DIV_2 (*) LL_RCC_PLLI2SQ_DIV_3 (*) LL_RCC_PLLI2SQ_DIV_4 (*) LL_RCC_PLLI2SQ_DIV_5 (*) LL_RCC_PLLI2SQ_DIV_6 (*) LL_RCC_PLLI2SQ_DIV_7 (*) LL_RCC_PLLI2SQ_DIV_8 (*) LL_RCC_PLLI2SQ_DIV_9 (*) LL_RCC_PLLI2SQ_DIV_10 (*) LL_RCC_PLLI2SQ_DIV_11 (*) LL_RCC_PLLI2SQ_DIV_12 (*) LL_RCC_PLLI2SQ_DIV_13 (*) LL_RCC_PLLI2SQ_DIV_14 (*) LL_RCC_PLLI2SQ_DIV_15 (*) LL_RCC_PLLI2SR_DIV_2 (*) LL_RCC_PLLI2SR_DIV_3 (*) LL_RCC_PLLI2SR_DIV_4 (*) LL_RCC_PLLI2SR_DIV_5 (*) LL_RCC_PLLI2SR_DIV_6 (*) LL_RCC_PLLI2SR_DIV_7 (*) (*) value not defined in all devices.
PLLDIVQ_R	This parameter can be one of the following values: LL_RCC_PLLI2SDIVQ_DIV_1 (*) LL_RCC_PLLI2SDIVQ_DIV_2 (*) LL_RCC_PLLI2SDIVQ_DIV_3 (*) LL_RCC_PLLI2SDIVQ_DIV_4 (*) LL_RCC_PLLI2SDIVQ_DIV_5 (*) LL_RCC_PLLI2SDIVQ_DIV_6 (*) LL_RCC_PLLI2SDIVQ_DIV_7 (*) LL_RCC_PLLI2SDIVQ_DIV_8 (*) LL_RCC_PLLI2SDIVQ_DIV_9 (*) LL_RCC_PLLI2SDIVQ_DIV_10 (*) LL_RCC_PLLI2SDIVQ_DIV_11 (*) LL_RCC_PLLI2SDIVQ_DIV_12 (*) LL_RCC_PLLI2SDIVQ_DIV_13 (*) LL_RCC_PLLI2SDIVQ_DIV_14 (*) LL_RCC_PLLI2SDIVQ_DIV_15 (*) LL_RCC_PLLI2SDIVQ_DIV_16 (*) LL_RCC_PLLI2SDIVQ_DIV_17 (*) LL_RCC_PLLI2SDIVQ_DIV_18 (*) LL_RCC_PLLI2SDIVQ_DIV_19 (*) LL_RCC_PLLI2SDIVQ_DIV_20 (*) LL_RCC_PLLI2SDIVQ_DIV_21 (*) LL_RCC_PLLI2SDIVQ_DIV_22 (*) LL_RCC_PLLI2SDIVQ_DIV_23 (*) LL_RCC_PLLI2SDIVQ_DIV_24 (*) LL_RCC_PLLI2SDIVQ_DIV_25 (*) LL_RCC_PLLI2SDIVQ_DIV_26 (*) LL_RCC_PLLI2SDIVQ_DIV_27 (*) LL_RCC_PLLI2SDIVQ_DIV_28 (*) LL_RCC_PLLI2SDIVQ_DIV_29 (*) LL_RCC_PLLI2SDIVQ_DIV_30 (*) LL_RCC_PLLI2SDIVQ_DIV_31 (*) LL_RCC_PLLI2SDIVQ_DIV_32 (*) LL_RCC_PLLI2SDIVR_DIV_1 (*) LL_RCC_PLLI2SDIVR_DIV_2 (*) LL_RCC_PLLI2SDIVR_DIV_3 (*) LL_RCC_PLLI2SDIVR_DIV_4 (*) LL_RCC_PLLI2SDIVR_DIV_5 (*) LL_RCC_PLLI2SDIVR_DIV_6 (*) LL_RCC_PLLI2SDIVR_DIV_7 (*) LL_RCC_PLLI2SDIVR_DIV_8 (*) LL_RCC_PLLI2SDIVR_DIV_9 (*) LL_RCC_PLLI2SDIVR_DIV_10 (*) LL_RCC_PLLI2SDIVR_DIV_11 (*) LL_RCC_PLLI2SDIVR_DIV_12 (*) LL_RCC_PLLI2SDIVR_DIV_13 (*) LL_RCC_PLLI2SDIVR_DIV_14 (*) LL_RCC_PLLI2SDIVR_DIV_15 (*) LL_RCC_PLLI2SDIVR_DIV_16 (*) LL_RCC_PLLI2SDIVR_DIV_17 (*) LL_RCC_PLLI2SDIVR_DIV_18 (*) LL_RCC_PLLI2SDIVR_DIV_19 (*) LL_RCC_PLLI2SDIVR_DIV_20 (*) LL_RCC_PLLI2SDIVR_DIV_21 (*) LL_RCC_PLLI2SDIVR_DIV_22 (*) LL_RCC_PLLI2SDIVR_DIV_23 (*) LL_RCC_PLLI2SDIVR_DIV_24 (*) LL_RCC_PLLI2SDIVR_DIV_25 (*) LL_RCC_PLLI2SDIVR_DIV_26 (*) LL_RCC_PLLI2SDIVR_DIV_27 (*) LL_RCC_PLLI2SDIVR_DIV_28 (*) LL_RCC_PLLI2SDIVR_DIV_29 (*) LL_RCC_PLLI2SDIVR_DIV_30 (*) LL_RCC_PLLI2SDIVR_DIV_31 (*) (*) value not defined in all devices.

Return values

None

Definition at line 5339 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLI2S_ConfigDomain_SPDIFRX()

__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX	(	uint32_t	Source,
		uint32_t	PLLM,
		uint32_t	PLLN,
		uint32_t	PLLP
	)

Configure PLLI2S used for SPDIFRX domain clock.

Note

PLL Source and PLLM Divider can be written only when PLL, PLLI2S and PLLSAI(*) are disabled

PLLN/PLLP can be written only when PLLI2S is disabled

This can be selected for SPDIFRX @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX

Parameters

Source	This parameter can be one of the following values: LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE
PLLM	This parameter can be one of the following values: LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLI2SM_DIV_63
PLLN	Between 50 and 432
PLLP	This parameter can be one of the following values: LL_RCC_PLLI2SP_DIV_2 LL_RCC_PLLI2SP_DIV_4 LL_RCC_PLLI2SP_DIV_6 LL_RCC_PLLI2SP_DIV_8

Return values

None

Definition at line 5559 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLI2S_Disable()

__STATIC_INLINE void LL_RCC_PLLI2S_Disable

(

void

)

Disable PLLI2S @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable.

Return values

None

Definition at line 5145 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLI2S_Enable()

__STATIC_INLINE void LL_RCC_PLLI2S_Enable

(

void

)

Enable PLLI2S @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable.

Return values

None

Definition at line 5135 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLI2S_GetDivider()

__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider

(

void

)

Get division factor for PLLI2S input clock @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider
PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider.

Return values

Returned

value can be one of the following values: LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLI2SM_DIV_63

Definition at line 5905 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLI2S_GetDIVQ()

__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ

(

void

)

Get I2SPLL division factor for PLLI2SDIVQ.

Note

used PLLSAICLK selected (SAI clock) @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ

Return values

Returned

value can be one of the following values: LL_RCC_PLLI2SDIVQ_DIV_1 LL_RCC_PLLI2SDIVQ_DIV_2 LL_RCC_PLLI2SDIVQ_DIV_3 LL_RCC_PLLI2SDIVQ_DIV_4 LL_RCC_PLLI2SDIVQ_DIV_5 LL_RCC_PLLI2SDIVQ_DIV_6 LL_RCC_PLLI2SDIVQ_DIV_7 LL_RCC_PLLI2SDIVQ_DIV_8 LL_RCC_PLLI2SDIVQ_DIV_9 LL_RCC_PLLI2SDIVQ_DIV_10 LL_RCC_PLLI2SDIVQ_DIV_11 LL_RCC_PLLI2SDIVQ_DIV_12 LL_RCC_PLLI2SDIVQ_DIV_13 LL_RCC_PLLI2SDIVQ_DIV_14 LL_RCC_PLLI2SDIVQ_DIV_15 LL_RCC_PLLI2SDIVQ_DIV_16 LL_RCC_PLLI2SDIVQ_DIV_17 LL_RCC_PLLI2SDIVQ_DIV_18 LL_RCC_PLLI2SDIVQ_DIV_19 LL_RCC_PLLI2SDIVQ_DIV_20 LL_RCC_PLLI2SDIVQ_DIV_21 LL_RCC_PLLI2SDIVQ_DIV_22 LL_RCC_PLLI2SDIVQ_DIV_23 LL_RCC_PLLI2SDIVQ_DIV_24 LL_RCC_PLLI2SDIVQ_DIV_25 LL_RCC_PLLI2SDIVQ_DIV_26 LL_RCC_PLLI2SDIVQ_DIV_27 LL_RCC_PLLI2SDIVQ_DIV_28 LL_RCC_PLLI2SDIVQ_DIV_29 LL_RCC_PLLI2SDIVQ_DIV_30 LL_RCC_PLLI2SDIVQ_DIV_31 LL_RCC_PLLI2SDIVQ_DIV_32

Definition at line 5787 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLI2S_GetDIVR()

__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR

(

void

)

Get I2SPLL division factor for PLLI2SDIVR.

Note

used PLLSAICLK selected (SAI clock) @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR

Return values

Returned

value can be one of the following values: LL_RCC_PLLI2SDIVR_DIV_1 LL_RCC_PLLI2SDIVR_DIV_2 LL_RCC_PLLI2SDIVR_DIV_3 LL_RCC_PLLI2SDIVR_DIV_4 LL_RCC_PLLI2SDIVR_DIV_5 LL_RCC_PLLI2SDIVR_DIV_6 LL_RCC_PLLI2SDIVR_DIV_7 LL_RCC_PLLI2SDIVR_DIV_8 LL_RCC_PLLI2SDIVR_DIV_9 LL_RCC_PLLI2SDIVR_DIV_10 LL_RCC_PLLI2SDIVR_DIV_11 LL_RCC_PLLI2SDIVR_DIV_12 LL_RCC_PLLI2SDIVR_DIV_13 LL_RCC_PLLI2SDIVR_DIV_14 LL_RCC_PLLI2SDIVR_DIV_15 LL_RCC_PLLI2SDIVR_DIV_16 LL_RCC_PLLI2SDIVR_DIV_17 LL_RCC_PLLI2SDIVR_DIV_18 LL_RCC_PLLI2SDIVR_DIV_19 LL_RCC_PLLI2SDIVR_DIV_20 LL_RCC_PLLI2SDIVR_DIV_21 LL_RCC_PLLI2SDIVR_DIV_22 LL_RCC_PLLI2SDIVR_DIV_23 LL_RCC_PLLI2SDIVR_DIV_24 LL_RCC_PLLI2SDIVR_DIV_25 LL_RCC_PLLI2SDIVR_DIV_26 LL_RCC_PLLI2SDIVR_DIV_27 LL_RCC_PLLI2SDIVR_DIV_28 LL_RCC_PLLI2SDIVR_DIV_29 LL_RCC_PLLI2SDIVR_DIV_30 LL_RCC_PLLI2SDIVR_DIV_31

Definition at line 5831 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLI2S_GetMainSource()

__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource

(

void

)

Get the oscillator used as PLL clock source. @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource
PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource.

Return values

Returned

value can be one of the following values: LL_RCC_PLLSOURCE_HSI LL_RCC_PLLSOURCE_HSE LL_RCC_PLLI2SSOURCE_PIN (*) (*) value not defined in all devices.

Definition at line 5925 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLI2S_GetN()

__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN

(

void

)

Get I2SPLL multiplication factor for VCO @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN.

Return values

Between

50/192(*) and 432 (*) value not defined in all devices.

Definition at line 5683 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLI2S_GetP()

__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP

(

void

)

Get I2SPLL division factor for PLLI2SP.

Note

used for PLLSPDIFRXCLK (SPDIFRX clock) @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP

Return values

Returned

value can be one of the following values: LL_RCC_PLLI2SP_DIV_2 LL_RCC_PLLI2SP_DIV_4 LL_RCC_PLLI2SP_DIV_6 LL_RCC_PLLI2SP_DIV_8

Definition at line 5742 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLI2S_GetQ()

__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ

(

void

)

Get I2SPLL division factor for PLLI2SQ @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ.

Return values

Returned

value can be one of the following values: LL_RCC_PLLI2SQ_DIV_2 LL_RCC_PLLI2SQ_DIV_3 LL_RCC_PLLI2SQ_DIV_4 LL_RCC_PLLI2SQ_DIV_5 LL_RCC_PLLI2SQ_DIV_6 LL_RCC_PLLI2SQ_DIV_7 LL_RCC_PLLI2SQ_DIV_8 LL_RCC_PLLI2SQ_DIV_9 LL_RCC_PLLI2SQ_DIV_10 LL_RCC_PLLI2SQ_DIV_11 LL_RCC_PLLI2SQ_DIV_12 LL_RCC_PLLI2SQ_DIV_13 LL_RCC_PLLI2SQ_DIV_14 LL_RCC_PLLI2SQ_DIV_15

Definition at line 5708 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLI2S_GetR()

__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR

(

void

)

Get I2SPLL division factor for PLLI2SR.

Note

used for PLLI2SCLK (I2S clock) @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR

Return values

Returned

value can be one of the following values: LL_RCC_PLLI2SR_DIV_2 LL_RCC_PLLI2SR_DIV_3 LL_RCC_PLLI2SR_DIV_4 LL_RCC_PLLI2SR_DIV_5 LL_RCC_PLLI2SR_DIV_6 LL_RCC_PLLI2SR_DIV_7

Definition at line 5726 of file stm32f4xx_ll_rcc.h.

LL_RCC_PLLI2S_IsReady()

__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady

(

void

)

Check if PLLI2S Ready @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady.

Return values

State

of bit (1 or 0).

Definition at line 5155 of file stm32f4xx_ll_rcc.h.