Initialization and Configuration functions. More...

Collaboration diagram for Initialization and de-initialization functions:

Functions
HAL_StatusTypeDef	HAL_RCC_DeInit (void)
	Resets the RCC clock configuration to the default reset state. More...

HAL_StatusTypeDef	HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)
	Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef. More...

HAL_StatusTypeDef	HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
	Initializes the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct. More...

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
           ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]
      This section provides functions allowing to configure the internal/external oscillators
      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
       and APB2).

    [..] Internal/external clock and PLL configuration
         (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
             the PLL as System clock source.

         (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
             clock source.

         (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
             through the PLL as System clock source. Can be used also as RTC clock source.

         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.

         (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
           (++) The first output is used to generate the high speed system clock (up to 168 MHz)
           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
                the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).

         (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
             and if a HSE clock failure occurs(HSE used directly or through PLL as System
             clock source), the System clocks automatically switched to HSI and an interrupt
             is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
             (Non-Maskable Interrupt) exception vector.

         (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
             clock (through a configurable prescaler) on PA8 pin.

         (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
             clock (through a configurable prescaler) on PC9 pin.

    [..] System, AHB and APB busses clocks configuration
         (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
             HSE and PLL.
             The AHB clock (HCLK) is derived from System clock through configurable
             prescaler and used to clock the CPU, memory and peripherals mapped
             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
             from AHB clock through configurable prescalers and used to clock
             the peripherals mapped on these busses. You can use
             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.

         (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
             frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
             Depending on the device voltage range, the maximum frequency should
             be adapted accordingly (refer to the product datasheets for more details).

         (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices,
             the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
             Depending on the device voltage range, the maximum frequency should
             be adapted accordingly (refer to the product datasheets for more details).

         (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
             PCLK2 84 MHz and PCLK1 42 MHz.
             Depending on the device voltage range, the maximum frequency should
             be adapted accordingly (refer to the product datasheets for more details).

         (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
             PCLK2 100 MHz and PCLK1 50 MHz.
             Depending on the device voltage range, the maximum frequency should
             be adapted accordingly (refer to the product datasheets for more details).

Function Documentation

◆ HAL_RCC_ClockConfig()

HAL_StatusTypeDef HAL_RCC_ClockConfig	(	RCC_ClkInitTypeDef *	RCC_ClkInitStruct,
		uint32_t	FLatency
	)

Initializes the CPU, AHB and APB busses clocks according to the specified parameters in the RCC_ClkInitStruct.

Parameters

RCC_ClkInitStruct	pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC peripheral.
FLatency	FLASH Latency, this parameter depend on device selected

Note: The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated by HAL_RCC_GetHCLKFreq() function called within this function; The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).; A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready.; Depending on the device voltage range, the software has to set correctly HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency (for more details refer to section above "Initialization/de-initialization functions")

Return values

None

Definition at line 591 of file stm32f4xx_hal_rcc.c.

◆ HAL_RCC_DeInit()

__weak HAL_StatusTypeDef HAL_RCC_DeInit ( void )

Resets the RCC clock configuration to the default reset state.

Note

The default reset state of the clock configuration is given below:

HSI ON and used as system clock source
HSE and PLL OFF
AHB, APB1 and APB2 prescaler set to 1.
CSS, MCO1 and MCO2 OFF
All interrupts disabled

This function doesn't modify the configuration of the

Peripheral clocks
LSI, LSE and RTC clocks

Return values

HAL status

Definition at line 200 of file stm32f4xx_hal_rcc.c.

◆ HAL_RCC_OscConfig()

__weak HAL_StatusTypeDef HAL_RCC_OscConfig ( RCC_OscInitTypeDef * RCC_OscInitStruct )

Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef.

Parameters

RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC Oscillators.

Note: The PLL is not disabled when used as system clock.; Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this API. User should request a transition to LSE Off first and then LSE On or LSE Bypass.; Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this API. User should request a transition to HSE Off first and then HSE On or HSE Bypass.

Return values

HAL status

Definition at line 219 of file stm32f4xx_hal_rcc.c.

Functions

Detailed Description

Function Documentation

◆ HAL_RCC_ClockConfig()

◆ HAL_RCC_DeInit()

◆ HAL_RCC_OscConfig()